IEEE Std 1800-2009: IEEE Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language

IEEE Std 1800-2009 cover page......Page 1
IEEE Std 1800-2009 title page......Page 3
Copyrights......Page 6
Patents......Page 7
Participants......Page 8
Contents......Page 11
List of figures......Page 25
List of tables......Page 29
List of syntax excerpts......Page 33
Part One: Design and Verification Constructs......Page 39
1.2 Purpose......Page 40
1.5 Conventions used in this standard......Page 41
1.6 Syntactic description......Page 42
1.8 Contents of this standard......Page 43
1.11 Prerequisites......Page 46
2. Normative references......Page 47
3.3 Modules......Page 49
3.4 Programs......Page 50
3.5 Interfaces......Page 51
3.9 Packages......Page 52
3.11 Overview of hierarchy......Page 53
3.12.1 Compilation units......Page 54
3.13 Name spaces......Page 56
3.14 Simulation time units and precision......Page 57
3.14.2.1 The `timescale compiler directive......Page 58
3.14.2.3 Precedence of timeunit, timeprecision and `timescale......Page 59
3.14.3 Simulation time unit......Page 60
4.3 Event simulation......Page 61
4.4 The stratified event scheduler......Page 62
4.4.2.5 Observed events region......Page 63
4.4.3.1 Preponed PLI region......Page 64
4.4.3.10 Postponed PLI region......Page 65
4.6 Determinism......Page 67
4.9 Scheduling implication of assignments......Page 68
4.9.5 Switch (transistor) processing......Page 69
4.10 The PLI callback control points......Page 70
5.5 Operators......Page 71
5.6.3 System tasks and system functions......Page 72
5.7 Numbers......Page 73
5.7.1 Integer literal constants......Page 75
5.7.2 Real literal constants......Page 77
5.9 String literals......Page 78
5.9.1 Special characters in strings......Page 79
5.10 Structure literals......Page 80
5.12 Attributes......Page 81
5.13 Built-in methods......Page 83
6.3.2 Strengths......Page 85
6.4 Singular and aggregate types......Page 86
6.5 Nets and variables......Page 87
6.6 Net types......Page 88
6.6.3 Wired nets......Page 89
6.6.4 Trireg net......Page 90
6.6.4.1 Capacitive networks......Page 91
6.6.4.2 Ideal capacitive state and charge decay......Page 93
6.7 Net declarations......Page 94
6.8 Variable declarations......Page 96
6.9.1 Specifying vectors......Page 98
6.10 Implicit declarations......Page 99
6.11.3 Signed and unsigned integer types......Page 100
6.14 Chandle data type......Page 101
6.16 String data type......Page 102
6.16.4 Toupper()......Page 105
6.16.9 Atoi(), atohex(), atooct(), atobin()......Page 106
6.17 Event data type......Page 107
6.18 User-defined types......Page 108
6.19 Enumerations......Page 109
6.19.2 Enumerated type ranges......Page 111
6.19.3 Type checking......Page 112
6.19.5 Enumerated type methods......Page 113
6.19.5.6 Name()......Page 114
6.20.1 Parameter declaration syntax......Page 115
6.20.2 Value parameters......Page 117
6.20.2.1 $ as a parameter value......Page 118
6.20.3 Type parameters......Page 119
6.20.5 Specify parameters......Page 120
6.20.6 Const constants......Page 121
6.21 Scope and lifetime......Page 122
6.22.1 Matching types......Page 124
6.22.2 Equivalent types......Page 125
6.22.3 Assignment compatible......Page 126
6.23 Type operator......Page 127
6.24.1 Cast operator......Page 128
6.24.2 $cast dynamic casting......Page 130
6.24.3 Bit-stream casting......Page 131
7.2 Structures......Page 135
7.2.1 Packed structures......Page 136
7.3 Unions......Page 137
7.3.1 Packed unions......Page 138
7.3.2 Tagged unions......Page 139
7.4 Packed and unpacked arrays......Page 140
7.4.2 Unpacked arrays......Page 141
7.4.5 Multidimensional arrays......Page 142
7.4.6 Indexing and slicing of arrays......Page 143
7.5 Dynamic arrays......Page 144
7.5.1 New[ ]......Page 145
7.5.3 Delete()......Page 146
7.6 Array assignments......Page 147
7.7 Arrays as arguments to subroutines......Page 148
7.8 Associative arrays......Page 149
7.8.2 String index......Page 150
7.8.6 Accessing invalid indices......Page 151
7.9.2 Delete()......Page 152
7.9.5 Last()......Page 153
7.9.8 Arguments to Traversal Methods......Page 154
7.10 Queues......Page 155
7.10.1 Queue operators......Page 156
7.10.2.4 Pop_front()......Page 157
7.10.4 Updating a queue using assignment and unpacked array concatenation......Page 158
7.12 Array manipulation methods......Page 159
7.12.1 Array locator methods......Page 160
7.12.2 Array ordering methods......Page 161
7.12.3 Array reduction methods......Page 162
7.12.4 Iterator index querying......Page 163
8.2 Overview......Page 165
8.3 Syntax......Page 166
8.4 Objects (class instance)......Page 167
8.6 Object methods......Page 168
8.7 Constructors......Page 169
8.8 Static class properties......Page 170
8.10 This......Page 171
8.11 Assignment, renaming, and copying......Page 172
8.12 Inheritance and subclasses......Page 173
8.13 Overridden members......Page 174
8.15 Casting......Page 175
8.17 Data hiding and encapsulation......Page 176
8.18 Constant class properties......Page 177
8.19 Virtual methods......Page 178
8.21 Polymorphism: dynamic method lookup......Page 179
8.22 Class scope resolution operator ::......Page 180
8.23 Out-of-block declarations......Page 182
8.24 Parameterized classes......Page 183
8.24.1 Class resolution operator for parameterized classes......Page 185
8.25 Typedef class......Page 186
8.27 Memory management......Page 187
9.2 Structured procedures......Page 189
9.2.2.1 General purpose always procedure......Page 190
9.2.2.2.2 always_comb compared to always @*......Page 191
9.2.3 Final procedures......Page 192
9.3.1 Sequential blocks......Page 193
9.3.2 Parallel blocks......Page 194
9.3.3 Statement block start and finish times......Page 196
9.3.4 Block names......Page 197
9.3.5 Statement labels......Page 198
9.4 Procedural timing controls......Page 199
9.4.2 Event control......Page 200
9.4.2.2 Implicit event_expression list......Page 202
9.4.2.3 Conditional event controls......Page 203
9.4.3 Level-sensitive event control......Page 204
9.4.4 Level-sensitive sequence controls......Page 205
9.4.5 Intra-assignment timing controls......Page 206
9.5 Process execution threads......Page 208
9.6.1 Wait fork statement......Page 209
9.6.2 Disable statement......Page 210
9.6.3 Disable fork statement......Page 212
9.7 Fine-grain process control......Page 213
10.2 Overview......Page 215
10.3.1 The net declaration assignment......Page 216
10.3.2 The continuous assignment statement......Page 217
10.3.3 Continuous assignment delays......Page 218
10.4 Procedural assignments......Page 219
10.4.2 Nonblocking procedural assignments......Page 220
10.6 Procedural continuous assignments......Page 224
10.6.2 The force and release procedural statements......Page 225
10.7 Assignment extension and truncation......Page 226
10.8 Assignment-like contexts......Page 227
10.9 Assignment patterns......Page 228
10.9.1 Array assignment patterns......Page 230
10.9.2 Structure assignment patterns......Page 231
10.10 Unpacked array concatenation......Page 232
10.10.2 Relationship with other constructs that use concatenation syntax......Page 233
10.10.3 Nesting of unpacked array concatenations......Page 234
10.11 Net aliasing......Page 235
11.2 Overview......Page 237
11.3 Operators......Page 238
11.3.1 Operators with real operands......Page 239
11.3.2 Operator precedence......Page 240
11.3.4 Operations on logic (4-state) and bit (2-state) types......Page 241
11.4.1 Assignment operators......Page 242
11.4.3 Arithmetic operators......Page 243
11.4.3.1 Arithmetic expressions with unsigned and signed types......Page 245
11.4.4 Relational operators......Page 246
11.4.6 Wildcard equality operators......Page 247
11.4.7 Logical operators......Page 248
11.4.8 Bitwise operators......Page 249
11.4.9 Reduction operators......Page 250
11.4.11 Conditional operator......Page 252
11.4.12 Concatenation operators......Page 254
11.4.12.1 Replication operator......Page 255
11.4.13 Set membership operator......Page 256
11.4.14 Streaming operators (pack/unpack)......Page 257
11.4.14.1 Concatenation of stream_expressions......Page 258
11.4.14.3 Streaming concatenation as an assignment target (unpack)......Page 259
11.4.14.4 Streaming dynamically sized data......Page 260
11.5.1 Vector bit-select and part-select addressing......Page 262
11.5.2 Array and memory addressing......Page 264
11.6 Expression bit lengths......Page 265
11.6.1 Rules for expression bit lengths......Page 266
11.6.2 Example of expression bit-length problem......Page 267
11.7 Signed expressions......Page 268
11.8.2 Steps for evaluating an expression......Page 269
11.9 Tagged union expressions and member access......Page 270
11.10.2 String literal value padding and potential problems......Page 272
11.11 Operator overloading......Page 273
11.12 Minimum, typical, and maximum delay expressions......Page 275
11.13 Let construct......Page 276
12.3 Syntax......Page 283
12.4 Conditional if–else statement......Page 284
12.4.1 if–else–if construct......Page 285
12.4.2 unique-if, unique0-if, and priority-if......Page 286
12.4.2.1 Violation reports generated by unique-if, unique0-if, and priority-if constructs......Page 287
12.4.2.2 If statement violation reports and multiple processes......Page 288
12.5 Case statement......Page 289
12.5.2 Constant expression in case statement......Page 291
12.5.3 unique-case, unique0-case, and priority-case......Page 292
12.5.4 Set membership case statement......Page 293
12.6 Pattern matching conditional statements......Page 294
12.6.1 Pattern matching in case statements......Page 295
12.6.2 Pattern matching in if statements......Page 297
12.7 Loop statements......Page 298
12.7.1 The for-loop......Page 299
12.7.3 The foreach loop......Page 300
12.7.4 The while loop......Page 301
12.8 Jump statements......Page 302
13.3 Tasks......Page 305
13.4 Functions......Page 309
13.4.2 Static and automatic functions......Page 312
13.4.3 Constant functions......Page 313
13.5 Subroutine calls and argument passing......Page 315
13.5.2 Pass by reference......Page 316
13.5.3 Default argument values......Page 318
13.5.4 Argument binding by name......Page 319
13.7 Task and function names......Page 320
14.3 Clocking block declaration......Page 321
14.4 Input and output skews......Page 323
14.5 Hierarchical expressions......Page 324
14.8 Multiple clocking blocks example......Page 325
14.9 Interfaces and clocking blocks......Page 326
14.11 Cycle delay: ##......Page 327
14.12 Default clocking......Page 328
14.13 Input sampling......Page 329
14.14 Global clocking......Page 330
14.16 Synchronous drives......Page 331
14.16.1 Drives and nonblocking assignments......Page 333
14.16.2 Driving clocking output signals......Page 334
15.3 Semaphores......Page 337
15.3.4 Try_get()......Page 338
15.4.2 Num()......Page 339
15.4.5 Get()......Page 340
15.4.8 Try_peek()......Page 341
15.5.1 Triggering an event......Page 342
15.5.3 Persistent trigger: triggered property......Page 343
15.5.4 Event sequencing: wait_order()......Page 344
15.5.5.1 Merging events......Page 345
15.5.5.3 Events comparison......Page 346
16.3 Immediate assertions......Page 347
16.4 Deferred assertions......Page 350
16.4.1 Deferred assertion reporting......Page 351
16.4.2 Deferred assertion flush points......Page 352
16.4.4 Disabling deferred assertions......Page 353
16.5 Concurrent assertions overview......Page 354
16.6.1 Operand types......Page 356
16.6.3 Operators......Page 357
16.7 Sequences......Page 358
16.8 Declaring sequences......Page 361
16.8.1 Typed formal arguments in sequence declarations......Page 365
16.8.2 Local variable formal arguments in sequence declarations......Page 367
16.9.2 Repetition in sequences......Page 369
16.9.3 Sampled value functions......Page 373
16.9.4 Global clocking past and future sampled value functions......Page 377
16.9.5 AND operation......Page 380
16.9.6 Intersection (AND with length restriction)......Page 382
16.9.7 OR operation......Page 383
16.9.8 First_match operation......Page 386
16.9.9 Conditions over sequences......Page 387
16.9.11 Detecting and using end point of a sequence......Page 389
16.10 Local variables......Page 391
16.11 Calling subroutines on match of a sequence......Page 397
16.13 Declaring properties......Page 398
16.13.1 Sequence property......Page 402
16.13.6 Implication......Page 403
16.13.7 Implies and iff properties......Page 407
16.13.9 Followed-by property......Page 408
16.13.10 Nexttime property......Page 409
16.13.11 Always property......Page 410
16.13.12 Until property......Page 411
16.13.13 Eventually property......Page 412
16.13.14 Abort properties......Page 414
16.13.15 Weak and strong operators......Page 415
16.13.16 Case......Page 416
16.13.17 Recursive properties......Page 417
16.13.20 Property examples......Page 421
16.13.21 Finite-length versus infinite-length behavior......Page 422
16.14.1 Multiclocked sequences......Page 423
16.14.2 Multiclocked properties......Page 425
16.14.3 Clock flow......Page 426
16.14.4 Examples......Page 427
16.14.5 Detecting and using end point of a sequence in multiclock context......Page 428
16.14.6 Sequence methods......Page 429
16.14.7 Local variable initialization assignments......Page 430
16.15 Concurrent assertions......Page 431
16.15.1 Assert statement......Page 432
16.15.2 Assume statement......Page 433
16.15.3 Cover statement......Page 435
16.15.5 Using concurrent assertion statements outside procedural code......Page 436
16.15.6 Embedding concurrent assertions in procedural code......Page 437
16.15.6.1 Arguments to procedural concurrent assertions......Page 439
16.15.6.2 Procedural assertion flush points......Page 441
16.15.6.3 Procedural concurrent assertions and glitches......Page 442
16.15.6.4 Disabling procedural concurrent assertions......Page 443
16.15.7 Inferred value functions......Page 444
16.15.8 Nonvacuous evaluations......Page 446
16.16 Disable iff resolution......Page 448
16.17 Clock resolution......Page 450
16.17.1 Semantic leading clocks for multiclocked sequences and properties......Page 454
16.18 Expect statement......Page 455
16.19 Clocking blocks and concurrent assertions......Page 457
17.2 Checker declaration......Page 459
17.3 Checker instantiation......Page 462
17.3.1 Behavior of instantiated checkers......Page 463
17.3.2 Nested checker instantiations......Page 464
17.5 Checker procedures......Page 465
17.6 Covergroups in checkers......Page 466
17.7 Checker variables......Page 467
17.7.1 Checker variable assignments......Page 470
17.7.2 Checker variable randomization with assumptions......Page 471
17.9 Complex checker example......Page 473
18.3 Concepts and usage......Page 475
18.4 Random variables......Page 478
18.4.1 Rand modifier......Page 479
18.5 Constraint blocks......Page 480
18.5.2 Constraint inheritance......Page 482
18.5.4 Distribution......Page 483
18.5.6 if–else constraints......Page 485
18.5.7.1 foreach iterative constraints......Page 486
18.5.8 Global constraints......Page 488
18.5.9 Variable ordering......Page 489
18.5.11 Functions in constraints......Page 491
18.5.12 Constraint guards......Page 492
18.6.1 Randomize()......Page 495
18.6.3 Behavior of randomization methods......Page 496
18.7 In-line constraints—randomize() with......Page 497
18.7.1 local:: Scope resolution......Page 498
18.8 Disabling random variables with rand_mode()......Page 499
18.9 Controlling constraints with constraint_mode()......Page 501
18.11 In-line random variable control......Page 502
18.12 Randomization of scope variables—std::randomize()......Page 503
18.12.1 Adding constraints to scope variables—std::randomize() with......Page 504
18.13.2 $urandom_range()......Page 505
18.14 Random stability......Page 506
18.14.2 Thread stability......Page 507
18.14.3 Object stability......Page 508
18.16 Random weighted case—randcase......Page 509
18.17 Random sequence generation—randsequence......Page 510
18.17.2 if–else production statements......Page 512
18.17.3 Case production statements......Page 513
18.17.5 Interleaving productions—rand join......Page 514
18.17.6 Aborting productions—break and return......Page 515
18.17.7 Value passing between productions......Page 516
19.2 Overview......Page 521
19.3 Defining the coverage model: covergroup......Page 522
19.4 Using covergroup in classes......Page 524
19.5 Defining coverage points......Page 526
19.5.1 Specifying bins for transitions......Page 529
19.5.3 Wildcard specification of coverage point bins......Page 533
19.5.5 Specifying Illegal coverage point values or transitions......Page 534
19.5.6 Value resolution......Page 535
19.6 Defining cross coverage......Page 536
19.6.1 Example of user-defined cross coverage and select expressions......Page 539
19.6.3 Specifying Illegal cross products......Page 540
19.7 Specifying coverage options......Page 541
19.7.1 Covergroup type options......Page 543
19.8 Predefined coverage methods......Page 545
19.8.1 Overriding the built-in sample method......Page 546
19.10 Organization of option and type_option members......Page 547
19.11 Coverage computation......Page 548
19.11.1 Coverpoint coverage computation......Page 549
19.11.2 Cross coverage computation......Page 550
19.11.3 Type coverage computation......Page 551
20.1 General......Page 553
20.3 Simulation time system functions......Page 554
20.3.3 $realtime......Page 555
20.4.1 $printtimescale......Page 556
20.4.2 $timeformat......Page 557
20.5 Conversion functions......Page 559
20.6.1 Type name function......Page 560
20.6.2 Expression size system function......Page 561
20.7 Array querying functions......Page 562
20.8 Math functions......Page 564
20.8.2 Real math functions......Page 565
20.10 Elaboration system tasks......Page 566
20.11 Assertion control system tasks......Page 568
20.12 Assertion action control system tasks......Page 569
20.13 Assertion system functions......Page 571
20.15.1 $random function......Page 572
20.15.2 Distribution functions......Page 573
20.16.2 $q_add......Page 574
20.16.6 Status codes......Page 575
20.17.1 Array types......Page 576
20.17.4 Logic array personality formats......Page 577
20.18.1 $system......Page 580
21.2.1 The display and write tasks......Page 581
21.2.1.1 Escape sequences for special characters......Page 582
21.2.1.2 Format specifications......Page 583
21.2.1.3 Size of displayed data......Page 586
21.2.1.4 Unknown and high-impedance values......Page 587
21.2.1.5 Strength format......Page 588
21.2.1.7 Assignment pattern format......Page 589
21.2.1.8 String format......Page 590
21.2.3 Continuous monitoring......Page 591
21.3.1 Opening and closing files......Page 592
21.3.2 File output system tasks......Page 593
21.3.3 Formatting data to a string......Page 595
21.3.4.2 Reading a line at a time......Page 596
21.3.4.3 Reading formatted data......Page 597
21.3.4.4 Reading binary data......Page 599
21.3.5 File positioning......Page 601
21.3.8 Detecting EOF......Page 602
21.4 Loading memory array data from a file......Page 603
21.4.1 Reading packed data......Page 604
21.4.3 File format considerations for multidimensional unpacked arrays......Page 605
21.5.1 Writing packed data......Page 606
21.6 Command line input......Page 607
21.7.1.1 Specifying name of dump file ($dumpfile)......Page 610
21.7.1.2 Specifying variables to be dumped ($dumpvars)......Page 611
21.7.1.3 Stopping and resuming the dump ($dumpoff/$dumpon)......Page 612
21.7.1.6 Reading dump file during simulation ($dumpflush)......Page 613
21.7.2.1 Syntax of 4-state VCD file......Page 614
21.7.2.2 Formats of variable values......Page 616
21.7.2.3 Description of keyword commands......Page 617
21.7.2.4 4-state VCD file format example......Page 619
21.7.3.1 Specifying dump file name and ports to be dumped ($dumpports)......Page 620
21.7.3.2 Stopping and resuming the dump ($dumpportsoff/$dumpportson)......Page 621
21.7.3.5 Reading dump file during simulation ($dumpportsflush)......Page 622
21.7.4 Format of extended VCD file......Page 623
21.7.4.1 Syntax of extended VCD file......Page 624
21.7.4.2 Extended VCD node information......Page 625
21.7.4.3.1 State characters......Page 627
21.7.4.4 Extended VCD file format example......Page 628
21.7.5 VCD SystemVerilog type mappings......Page 629
22.3 `resetall......Page 631
22.5 `define, `undef and `undefineall......Page 632
22.5.1 `define......Page 633
22.6 `ifdef, `else, `elsif, `endif, `ifndef......Page 638
22.7 `timescale......Page 641
22.8 `default_nettype......Page 642
22.11 `pragma......Page 643
22.12 `line......Page 644
22.13 `__FILE__ and `__LINE__......Page 645
22.14 `begin_keywords, `end_keywords......Page 646
22.14.1 Examples......Page 647
22.14.3 IEEE Std 1364-2001 keywords......Page 648
22.14.6 IEEE Std 1800-2005 keywords......Page 649
22.14.7 IEEE Std 1800-2009 keywords......Page 650
Part Two: Hierarchy Constructs......Page 651
23.2.1 Module header definition......Page 652
23.2.2.1 Non-ANSI style port declarations......Page 654
23.2.2.2 ANSI style list of port declarations......Page 657
23.2.2.3 Rules for determining port kind, data type and direction......Page 659
23.2.2.4 Default port values......Page 661
23.2.4 Module contents......Page 662
23.3.2 Module instantiation syntax......Page 664
23.3.2.1 Connecting module instance ports by ordered list......Page 666
23.3.2.2 Connecting module instance ports by name......Page 667
23.3.2.3 Connecting module instance using implicit named port connections (.name)......Page 668
23.3.2.4 Connecting module instances using wildcard named port connections ( .*)......Page 669
23.3.3.2 Port connection rules for variables......Page 670
23.3.3.5 Unpacked array ports and arrays of instances......Page 671
23.3.3.7 Port connections with dissimilar net types (net and port collapsing)......Page 672
23.3.3.8 Connecting signed values via ports......Page 673
23.4 Nested modules......Page 674
23.5 Extern modules......Page 675
23.6 Hierarchical names......Page 676
23.7 Member selects and hierarchical names......Page 679
23.8 Upwards name referencing......Page 680
23.9 Scope rules......Page 682
23.10 Overriding module parameters......Page 684
23.10.1 defparam statement......Page 686
23.10.2.1 Parameter value assignment by ordered list......Page 687
23.10.2.2 Parameter value assignment by name......Page 689
23.10.3 Parameter dependence......Page 690
23.10.4.2 Early resolution of hierarchical names......Page 691
23.11 Binding auxiliary code to scopes or instances......Page 692
24.3 The program construct......Page 697
24.3.1 Scheduling semantics of code in program constructs......Page 699
24.3.2 Operation of program port connections in the absence of clocking blocks......Page 700
24.5 Blocking tasks in cycle/event mode......Page 701
24.7 Program control tasks......Page 702
25.2 Overview......Page 703
25.3 Interface syntax......Page 704
25.3.1 Example without using interfaces......Page 705
25.3.2 Interface example using a named bundle......Page 706
25.3.3 Interface example using a generic bundle......Page 707
25.4 Ports in interfaces......Page 708
25.5 Modports......Page 709
25.5.2 Example of connecting port bundle......Page 711
25.5.3 Example of connecting port bundle to generic interface......Page 712
25.5.4 Modport expressions......Page 713
25.5.5 Clocking blocks and modports......Page 714
25.6 Interfaces and specify blocks......Page 715
25.7 Tasks and functions in interfaces......Page 716
25.7.2 Example of using tasks in modports......Page 717
25.7.3 Example of exporting tasks and functions......Page 719
25.7.4 Example of multiple task exports......Page 720
25.8 Parameterized interfaces......Page 722
25.9 Virtual interfaces......Page 724
25.9.2 Virtual interface modports and clocking blocks......Page 727
25.10 Access to interface objects......Page 729
26.2 Package declarations......Page 731
26.3 Referencing data in packages......Page 732
26.4 Using packages in module headers......Page 736
26.5 Search order rules......Page 737
26.6 Exporting imported names from packages......Page 739
26.7 The std built-in package......Page 740
27.3 Generate construct syntax......Page 743
27.4 Loop generate constructs......Page 745
27.5 Conditional generate constructs......Page 749
27.6 External names for unnamed generate blocks......Page 752
28.3 Gate and switch declaration syntax......Page 755
28.3.1 The gate type specification......Page 756
28.3.2 The drive strength specification......Page 757
28.3.6 Primitive instance connection list......Page 758
28.4 and, nand, nor, or, xor, and xnor gates......Page 761
28.5 buf and not gates......Page 762
28.6 bufif1, bufif0, notif1, and notif0 gates......Page 763
28.7 MOS switches......Page 764
28.8 Bidirectional pass switches......Page 765
28.9 CMOS switches......Page 766
28.11 Logic strength modeling......Page 767
28.12.1 Combined signals of unambiguous strength......Page 769
28.12.2 Ambiguous strengths: sources and combinations......Page 770
28.12.3 Ambiguous strength signals and unambiguous signals......Page 775
28.12.4 Wired logic net types......Page 779
28.15.2 trireg strength......Page 782
28.16 Gate and net delays......Page 783
28.16.1 min:typ:max delays......Page 784
28.16.2.2 Delay specification for charge decay time......Page 785
29.3 UDP definition......Page 787
29.3.4 UDP state table......Page 789
29.3.6 Summary of symbols......Page 790
29.4 Combinational UDPs......Page 791
29.6 Edge-sensitive sequential UDPs......Page 792
29.7 Sequential UDP initialization......Page 793
29.8 UDP instances......Page 795
29.9 Mixing level-sensitive and edge-sensitive descriptions......Page 796
29.10 Level-sensitive dominance......Page 797
30.3 Specify block declaration......Page 799
30.4 Module path declarations......Page 800
30.4.2 Simple module paths......Page 801
30.4.3 Edge-sensitive paths......Page 802
30.4.4.1 Conditional expression......Page 803
30.4.4.2 Simple state-dependent paths......Page 804
30.4.4.3 Edge-sensitive state-dependent paths......Page 805
30.4.4.4 The ifnone condition......Page 806
30.4.5 Full connection and parallel connection paths......Page 807
30.4.7 Module path polarity......Page 808
30.5 Assigning delays to module paths......Page 809
30.5.1 Specifying transition delays on module paths......Page 810
30.5.2 Specifying x transition delays......Page 812
30.6 Mixing module path delays and distributed delays......Page 813
30.7 Detailed control of pulse filtering behavior......Page 814
30.7.1 Specify block control of pulse limit values......Page 815
30.7.4 Detailed pulse control capabilities......Page 816
30.7.4.1 On-event versus on-detect pulse filtering......Page 817
30.7.4.2 Negative pulse detection......Page 818
31.2 Overview......Page 823
31.3.1 $setup......Page 826
31.3.2 $hold......Page 827
31.3.3 $setuphold......Page 828
31.3.4 $removal......Page 829
31.3.5 $recovery......Page 830
31.3.6 $recrem......Page 831
31.4.1 $skew......Page 833
31.4.2 $timeskew......Page 834
31.4.3 $fullskew......Page 836
31.4.4 $width......Page 839
31.4.5 $period......Page 840
31.4.6 $nochange......Page 841
31.5 Edge-control specifiers......Page 842
31.6 Notifiers: user-defined responses to timing violations......Page 843
31.7 Enabling timing checks with conditioned events......Page 845
31.8 Vector signals in timing checks......Page 846
31.9 Negative timing checks......Page 847
31.9.1 Requirements for accurate simulation......Page 848
31.9.2 Conditions in negative timing checks......Page 850
31.9.4 Option behavior......Page 851
32.4 Mapping of SDF constructs to SystemVerilog......Page 853
32.4.1 Mapping of SDF delay constructs to SystemVerilog declarations......Page 854
32.4.2 Mapping of SDF timing check constructs to SystemVerilog......Page 855
32.4.3 SDF annotation of specparams......Page 856
32.4.4 SDF annotation of interconnect delays......Page 857
32.5 Multiple annotations......Page 858
32.7 Pulse limit annotation......Page 859
32.9 Loading timing data from an SDF file......Page 860
33.2.1 Library notation......Page 863
33.3.1 Specifying libraries—the library map file......Page 864
33.3.1.1 File path resolution......Page 865
33.4 Configurations......Page 866
33.4.1.2 The default clause......Page 867
33.4.2 Hierarchical configurations......Page 868
33.4.3 Setting parameters in configurations......Page 869
33.5.1 Precompiling in a single-pass use model......Page 872
33.6 Configuration examples......Page 873
33.6.4 Using instance clause......Page 874
33.8 Library mapping examples......Page 875
33.8.3 Resolving multiple path specifications......Page 876
34.3 Processing protected envelopes......Page 879
34.3.1 Encryption......Page 880
34.4 Protect pragma directives......Page 881
34.5.2.2 Description......Page 883
34.5.5.2 Description......Page 884
34.5.8.2 Description......Page 885
34.5.9.2 Description......Page 886
34.5.11.2 Description......Page 887
34.5.12.2 Description......Page 888
34.5.14.2 Description......Page 889
34.5.17.1 Syntax......Page 890
34.5.19.2 Description......Page 891
34.5.21.2 Description......Page 892
34.5.22.2 Description......Page 893
34.5.25.2 Description......Page 894
34.5.27.2 Description......Page 895
34.5.29.2 Description......Page 896
34.5.31.2 Description......Page 897
34.5.32.2 Description......Page 898
Part Three: Application Programming Interfaces......Page 899
35.2.1 Tasks and functions......Page 900
35.3 Two layers of the DPI......Page 901
35.4 Global name space of imported and exported functions......Page 902
35.5.1.3 Special properties pure and context......Page 903
35.5.2 Pure functions......Page 904
35.5.3 Context tasks and functions......Page 905
35.5.4 Import declarations......Page 907
35.5.6 Types of formal arguments......Page 909
35.6 Calling imported functions......Page 910
35.6.1.1 WYSIWYG principle......Page 911
35.7 Exported functions......Page 912
35.9 Disabling DPI tasks and functions......Page 913
36.2 PLI purpose and history......Page 915
36.3.2 Overriding built-in system task and system function names......Page 916
36.8 VPI sizetf, compiletf and calltf routines......Page 917
36.9 PLI mechanism......Page 918
36.9.2 Registering simulation callbacks......Page 919
36.10.2 Function availability......Page 920
36.11 List of VPI routines by functional category......Page 921
36.12 VPI backwards compatibility features and limitations......Page 923
36.12.1 VPI Incompatibilities with other standard versions......Page 924
36.12.2.1 Mechanism 1: Compile-based binding to a compatibility mode......Page 925
36.12.3 Limitations of VPI compatibility mechanisms......Page 927
37.2.2 Handle release......Page 929
37.3 VPI object classifications......Page 930
37.3.1 Accessing object relationships and properties......Page 931
37.3.2 Object type properties......Page 932
37.3.4 Delays and values......Page 933
37.3.5 Expressions with side effects......Page 934
37.3.7 Lifetimes of objects......Page 935
37.4 Key to data model diagrams......Page 936
37.4.2 Diagram key for accessing properties......Page 937
37.4.3 Diagram key for traversing relationships......Page 938
37.5 Module......Page 939
37.8 Interface task or function declaration......Page 940
37.9 Program......Page 941
37.10 Instance......Page 942
37.11 Instance arrays......Page 944
37.12 Scope......Page 945
37.13 IO declaration......Page 946
37.14 Ports......Page 947
37.15 Reference objects......Page 948
37.16 Nets......Page 951
37.17 Variables......Page 955
37.18 Packed array variables......Page 958
37.19 Variable select......Page 959
37.21 Variable drivers and loads......Page 960
37.22 Object Range......Page 961
37.23 Typespec......Page 962
37.24 Structures and unions......Page 964
37.25 Named events......Page 965
37.26 Parameter, spec param, def param, param assign......Page 966
37.27 Class definition......Page 967
37.28 Class typespec......Page 968
37.29 Class variables and class objects......Page 970
37.30 Constraint, constraint ordering, distribution......Page 972
37.31 Primitive, prim term......Page 973
37.33 Intermodule path......Page 974
37.35 Module path, path term......Page 975
37.36 Timing check......Page 976
37.37 Task and function declaration......Page 977
37.38 Task and function call......Page 978
37.39 Frames......Page 980
37.41 Delay terminals......Page 981
37.42 Net drivers and loads......Page 982
37.43 Continuous assignment......Page 983
37.44 Clocking block......Page 984
37.45 Assertion......Page 985
37.46 Concurrent assertions......Page 986
37.47 Property declaration......Page 987
37.48 Property specification......Page 988
37.49 Sequence declaration......Page 989
37.50 Sequence expression......Page 990
37.51 Immediate assertions......Page 991
37.53 Let......Page 992
37.54 Simple expressions......Page 993
37.55 Expressions......Page 994
37.56 Atomic statement......Page 997
37.58 Process......Page 998
37.60 Event control......Page 999
37.63 Delay control......Page 1000
37.66 If, if–else......Page 1001
37.67 Case, pattern......Page 1002
37.70 Do-while, foreach......Page 1003
37.71 Alias statement......Page 1004
37.74 Assign statement, deassign, force, release......Page 1005
37.76 Time queue......Page 1006
37.77 Active time format......Page 1007
37.78 Attribute......Page 1008
37.79 Iterator......Page 1009
37.80 Generates......Page 1010
38.2 vpi_chk_error()......Page 1013
38.3 vpi_compare_objects()......Page 1014
38.4 vpi_control()......Page 1016
38.6 vpi_get()......Page 1017
38.8 vpi_get_cb_info()......Page 1018
38.9 vpi_get_data()......Page 1019
38.10 vpi_get_delays()......Page 1020
38.11 vpi_get_str()......Page 1022
38.12 vpi_get_systf_info()......Page 1023
38.13 vpi_get_time()......Page 1024
38.15 vpi_get_value()......Page 1025
38.16 vpi_get_value_array()......Page 1031
38.17 vpi_get_vlog_info()......Page 1035
38.18 vpi_handle()......Page 1036
38.20 vpi_handle_by_multi_index()......Page 1037
38.21 vpi_handle_by_name()......Page 1038
38.23 vpi_iterate()......Page 1039
38.24 vpi_mcd_close()......Page 1040
38.26 vpi_mcd_name()......Page 1041
38.27 vpi_mcd_open()......Page 1042
38.28 vpi_mcd_printf()......Page 1043
38.30 vpi_printf()......Page 1044
38.31 vpi_put_data()......Page 1045
38.32 vpi_put_delays()......Page 1047
38.34 vpi_put_value()......Page 1050
38.35 vpi_put_value_array()......Page 1053
38.36 vpi_register_cb()......Page 1057
38.36.1 Simulation event callbacks......Page 1058
38.36.1.2 Behavior by statement type......Page 1061
38.36.2 Simulation time callbacks......Page 1062
38.36.3 Simulator action or feature callbacks......Page 1063
38.37.1 System task and system function callbacks......Page 1065
38.37.3 Registering multiple system tasks and system functions......Page 1067
38.38 vpi_release_handle()......Page 1068
38.40 vpi_scan()......Page 1069
38.41 vpi_vprintf()......Page 1070
39.3.1 Obtaining assertion handles......Page 1071
39.4.1 Placing assertion system callbacks......Page 1072
39.4.2 Placing assertions callbacks......Page 1073
39.5.1 Assertion system control......Page 1076
39.5.2 Assertion control......Page 1077
39.5.3 VPI functions on deferred assertions and procedural concurrent assertions......Page 1079
40.2.2 Nomenclature......Page 1081
40.3.2.1 $coverage_control......Page 1082
40.3.2.3 $coverage_get......Page 1085
40.3.2.5 $coverage_save......Page 1086
40.4.3 Specifying concatenation that holds current state......Page 1087
40.4.7 Pragmas in one-line comments......Page 1088
40.5.2 Extensions to VPI enumerations......Page 1089
40.5.3 Obtaining coverage information......Page 1090
40.5.4 Controlling coverage......Page 1092
41. Data read API......Page 1095
Part Four: Annexes......Page 1097
A.1.2 SystemVerilog source text......Page 1098
A.1.3 Module parameters and ports......Page 1100
A.1.4 Module items......Page 1101
A.1.5 Configuration source text......Page 1102
A.1.8 Checker items......Page 1103
A.1.9 Class items......Page 1104
A.1.10 Constraints......Page 1105
A.2.1.2 Port declarations......Page 1106
A.2.2.1 Net and variable types......Page 1107
A.2.2.2 Strengths......Page 1108
A.2.4 Declaration assignments......Page 1109
A.2.6 Function declarations......Page 1110
A.2.8 Block item declarations......Page 1111
A.2.10 Assertion declarations......Page 1112
A.2.11 Covergroup declarations......Page 1116
A.3.1 Primitive instantiation and instances......Page 1117
A.3.4 Primitive gate and switch types......Page 1118
A.4.1.4 Checker instantiation......Page 1119
A.5.1 UDP declaration......Page 1120
A.5.4 UDP instantiation......Page 1121
A.6.3 Parallel and sequential blocks......Page 1122
A.6.5 Timing control statements......Page 1123
A.6.7 Case statements......Page 1124
A.6.7.1 Patterns......Page 1125
A.6.10 Assertion statements......Page 1126
A.6.11 Clocking block......Page 1127
A.7.1 Specify block declaration......Page 1128
A.7.4 Specify path delays......Page 1129
A.7.5.1 System timing check commands......Page 1130
A.7.5.2 System timing check command arguments......Page 1131
A.8.1 Concatenations......Page 1132
A.8.3 Expressions......Page 1133
A.8.4 Primaries......Page 1135
A.8.6 Operators......Page 1136
A.8.7 Numbers......Page 1137
A.9.3 Identifiers......Page 1138
A.10 Footnotes (normative)......Page 1140
Annex B (normative) Keywords......Page 1143
C.2.4 vpi_free_object()......Page 1145
C.4.1 Defparam statements......Page 1146
C.4.2 Procedural assign and deassign statements......Page 1147
D.2 $countdrivers......Page 1149
D.3 $getpattern......Page 1150
D.6 $list......Page 1151
D.8 $reset, $reset_count, and $reset_value......Page 1152
D.9 $save, $restart, and $incsave......Page 1153
D.13 $showvars......Page 1154
D.14 $sreadmemb and $sreadmemh......Page 1155
E.3 `default_trireg_strength......Page 1157
E.7 `delay_mode_zero......Page 1158
F.2 Overview......Page 1159
F.3.1 Clock control......Page 1160
F.3.2 Abstract grammars......Page 1161
F.3.3 Notations......Page 1162
F.3.4.2.3 Derived nonconsecutive repetition operators......Page 1163
F.3.4.3.7 Derived abort operators......Page 1164
F.3.4.6 Checker variable assignment......Page 1165
F.4.1.1 The rewriting algorithm......Page 1166
F.4.2 Rewriting local variable declaration assignments......Page 1168
F.5.1.1 Rewrite rules for sequences......Page 1170
F.5.2 Tight satisfaction without local variables......Page 1171
F.5.3.1 Neutral satisfaction......Page 1172
F.5.3.2 Weak and strong satisfaction by finite words......Page 1173
F.5.3.3 Vacuity......Page 1174
F.5.4 Local variable flow......Page 1175
F.5.5 Tight satisfaction with local variables......Page 1176
F.5.6.1 Neutral satisfaction......Page 1177
F.5.6.2 Weak and strong satisfaction by finite words......Page 1178
F.7 Recursive properties......Page 1179
G.4 Mailbox......Page 1183
G.6 Process......Page 1184
H.2 Overview......Page 1185
H.5 svdpi.h include file......Page 1186
H.6 Semantic constraints......Page 1187
H.6.5 Context and noncontext tasks and functions......Page 1188
H.6.7 Memory management......Page 1189
H.7.3 Data representation......Page 1190
H.7.4 Basic types......Page 1191
H.7.6 Mapping between SystemVerilog ranges and C ranges......Page 1192
H.8.2 Calling SystemVerilog tasks and functions from C......Page 1193
H.8.7 Input arguments......Page 1194
H.8.10 String arguments......Page 1195
H.9.1 Overview of DPI and VPI context......Page 1196
H.9.3 Working with DPI context tasks and functions in C code......Page 1197
H.9.4 Example 1—Using DPI context functions......Page 1199
H.9.5 Relationship between DPI and VPI......Page 1200
H.10.1.2 Canonical representation of packed arrays......Page 1201
H.10.2 Example 2—Simple packed array application......Page 1202
H.10.3 Example 3—Application with complex mix of types......Page 1203
H.11.3 Example 5—Using packed struct and union arguments......Page 1204
H.11.5 Utility functions for working with the canonical representation......Page 1205
H.12.1 Actual ranges......Page 1206
H.12.2 Array querying functions......Page 1207
H.12.4 Access to actual representation......Page 1208
H.12.6 Access to scalar elements (bit and logic)......Page 1209
H.12.8 Example 6—Two-dimensional open array......Page 1210
H.12.9 Example 7—Open array......Page 1211
H.13 SV3.1a-compatible access to packed data (deprecated functionality)......Page 1212
H.13.2 svdpi.h definitions for SV3.1a-style packed data processing......Page 1213
H.13.4 Example 9—Deprecated SV3.1a binary compatible application......Page 1215
H.13.6 Example 11—Deprecated SV3.1a binary compatible calls of export functions......Page 1216
I.3 Source code......Page 1219
J.2 Overview......Page 1229
J.4 Object code inclusion......Page 1230
J.4.2 Examples......Page 1231
K.2 Source code......Page 1233
L.2 Source code......Page 1251
M.2 Source code......Page 1255
N.2 Source code......Page 1265
O.3.1 Encryption input......Page 1273
O.4.1 Encryption input......Page 1274
O.5 Digital envelopes......Page 1275
O.5.2 Encryption output......Page 1276
Annex P (informative) Glossary......Page 1277
Annex Q (informative) Mapping of IEEE Std 1364-2005 and IEEE Std 1800-2005 clauses into IEEE Std 1800-2009......Page 1281
Annex R (informative) Bibliography......Page 1285