IA-32 Intel® Architecture Software Developer’s Manual. Volume 3: System Programming Guide

IA-32 Intel® Architecture Software Developer’s Manual, Vol ume 3 : System Programming Guide......Page 1
Disclaimer......Page 2
Contents......Page 3
Figures......Page 19
Tables......Page 23
1.1. IA-32 Processors Covered in this Manual......Page 29
1.2. Overview of the IA-32 Intel Architecture Software Developer’s Manual, Volume 3: SYSTEM PROGR.........Page 30
1.3. Overview of the IA-32 Intel Architecture Software Developer’s Manual, Volume 1: BASIC ARCHIT.........Page 32
1.4. Overview of the IA-32 Intel Architecture Software Developer’s Manual, Volume 2: INSTRUCTION .........Page 33
1.5.2. Reserved Bits and Software Compatibility......Page 34
1.5.3. Instruction Operands......Page 35
1.5.5. Segmented Addressing......Page 36
1.6. Related Literature......Page 37
2.1. Overview of the System-Level Architecture......Page 41
2.1.2. System Segments, Segment Descriptors, and Gates......Page 43
2.1.4. Interrupt and Exception Handling......Page 44
2.1.6. System Registers......Page 45
2.2. Modes of Operation......Page 46
2.3. System Flags and Fields in the EFLAGS Register......Page 47
2.4.1. Global Descriptor Table Register (GDTR)......Page 50
2.4.4. Task Register (TR)......Page 51
2.5. Control Registers......Page 52
2.6. System Instruction Summary......Page 58
2.6.1. Loading and Storing System Registers......Page 60
2.6.4. Invalidating Caches and TLBs......Page 61
2.6.6. Reading Performance-Monitoring and Time-Stamp Counters......Page 62
2.6.7. Reading and Writing Model-Specific Registers......Page 63
3.1. Memory Management Overview......Page 67
3.2.2. Protected Flat Model......Page 69
3.2.3. Multi-Segment Model......Page 71
3.4. Logical and Linear Addresses......Page 72
3.4.1. Segment Selectors......Page 73
3.4.2. Segment Registers......Page 74
3.4.3. Segment Descriptors......Page 75
3.4.3.1. Code- and Data-Segment Descriptor Types......Page 79
3.5. System Descriptor Types......Page 80
3.5.1. Segment Descriptor Tables......Page 81
3.6. Paging (Virtual Memory) Overview......Page 83
3.6.1. Paging Options......Page 84
3.6.2. Page Tables and Directories......Page 85
3.7.1. Linear Address Translation (4-KByte Pages)......Page 86
3.7.2. Linear Address Translation (4-MByte Pages)......Page 87
3.7.3. Mixing 4-KByte and 4-MByte Pages......Page 88
3.7.6. Page-Directory and Page-Table Entries......Page 89
3.8. 36-Bit Physical Addressing Using the PAE Paging Mechanism......Page 94
3.8.1. Linear Address Translation With PAE Enabled (4-KByte Pages)......Page 95
3.8.2. Linear Address Translation With PAE Enabled (2-MByte Pages)......Page 96
3.8.4. Page-Directory and Page-Table Entries With Extended Addressing Enabled......Page 97
3.9. 36-Bit Physical Addressing Using the PSE-36 Paging Mechanism......Page 100
3.10. Mapping Segments to Pages......Page 102
3.11. Translation Lookaside Buffers (TLBs)......Page 103
CHAPTER 4 Protection......Page 107
4.2. Fields and Flags Used for Segment-Level and Page-Level Protection......Page 108
4.3. Limit Checking......Page 111
4.4. Type Checking......Page 112
4.5. Privilege Levels......Page 113
4.6. Privilege Level Checking When Accessing Data Segments......Page 116
4.8. Privilege Level Checking When Transferring Program Control Between Code Segments......Page 118
4.8.1. Direct Calls or Jumps to Code Segments......Page 119
4.8.1.1. Accessing Nonconforming Code Segments......Page 120
4.8.1.2. Accessing Conforming Code Segments......Page 121
4.8.2. Gate Descriptors......Page 122
4.8.3. Call Gates......Page 123
4.8.4. Accessing a Code Segment Through a Call Gate......Page 124
4.8.5. Stack Switching......Page 127
4.8.6. Returning from a Called Procedure......Page 130
4.8.7. Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions......Page 131
4.9. Privileged Instructions......Page 132
4.10.1. Checking Access Rights (LAR Instruction)......Page 133
4.10.2. Checking Read/Write Rights (VERR and VERW Instructions)......Page 134
4.10.4. Checking Caller Access Privileges (ARPL Instruction)......Page 135
4.11. Page-Level Protection......Page 137
4.11.2. Restricting Addressable Domain......Page 138
4.11.5. Overrides to Page Protection......Page 139
4.12. Combining Page and Segment Protection......Page 140
5.1. Interrupt and Exception Overview......Page 143
5.3.1. External Interrupts......Page 144
5.3.3. Software-Generated Interrupts......Page 146
5.4.3. Machine-Check Exceptions......Page 147
5.6. Program or Task Restart......Page 148
5.8.1. Masking Maskable Hardware Interrupts......Page 150
5.8.2. Masking Instruction Breakpoints......Page 151
5.9. Priority Among Simultaneous Exceptions and Interrupts......Page 152
5.10. Interrupt Descriptor Table (IDT)......Page 153
5.11. IDT Descriptors......Page 154
5.12.1. Exception- or Interrupt-Handler Procedures......Page 156
5.12.1.1. Protection of Exception- and Interrupt-Handler Procedures......Page 158
5.12.1.2. Flag Usage By Exception- or Interrupt-Handler Procedure......Page 159
5.12.2. Interrupt Tasks......Page 160
5.13. Error Code......Page 161
5.14. Exception and Interrupt Reference......Page 162
6.1.1. Task Structure......Page 201
6.1.2. Task State......Page 202
6.1.3. Executing a Task......Page 203
6.2.1. Task-State Segment (TSS)......Page 204
6.2.2. TSS Descriptor......Page 207
6.2.3. Task Register......Page 208
6.2.4. Task-Gate Descriptor......Page 209
6.3. Task Switching......Page 212
6.4. Task Linking......Page 216
6.4.1. Use of Busy Flag To Prevent Recursive Task Switching......Page 217
6.5. Task Address Space......Page 218
6.5.1. Mapping Tasks to the Linear and Physical Address Spaces......Page 219
6.5.2. Task Logical Address Space......Page 220
6.6. 16-Bit Task-State Segment (TSS)......Page 221
CHAPTER 7 Multiple-Processor Management......Page 225
7.1. Locked Atomic Operations......Page 226
7.1.2. Bus Locking......Page 227
7.1.2.2. Software Controlled Bus Locking......Page 228
7.1.3. Handling Self- and Cross-Modifying Code......Page 230
7.2. Memory Ordering......Page 231
7.2.2. Memory Ordering Pentium 4, Intel Xeon, and P6 Family Processors......Page 232
7.2.3. Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors......Page 234
7.2.4. Strengthening or Weakening the Memory Ordering Model......Page 235
7.3. Propagation of Page Table and Page Directory Entry Changes to Multiple Processors......Page 237
7.4. Serializing Instructions......Page 238
7.5. Multiple-Processor (MP) Initialization......Page 239
7.5.2. MP Initialization Protocol Requirements and Restrictions for Intel Xeon Processors......Page 240
7.5.3. MP Initialization Protocol Algorithm for the Intel Xeon Processors......Page 241
7.5.4. MP Initialization Example......Page 242
7.5.4.1. Typical BSP Initialization Sequence......Page 243
7.5.4.2. Typical AP Initialization Sequence......Page 245
7.5.5. Identifying the Processors in an MP System......Page 246
7.6.1. Implementation of Hyper-Threading Technology in IA-32 Processors......Page 247
7.6.2.1. IA-32 Architectural State of a Logical Processor......Page 248
7.6.2.3. Memory Type Range Registers (MTRR)......Page 250
7.6.2.6. Debug Registers and Extensions......Page 251
7.6.2.11. Microcode Update Resources......Page 252
7.6.3.1. Processor Caches......Page 253
7.6.4.1. STPCLK#......Page 254
7.6.5. Detecting Hyper-Threading Technology......Page 255
7.6.7. Executing Multiple Threads on an IA-32 Processor With Hyper-Threading Technology......Page 256
7.6.8. Handling Interrupts on an IA-32 Processor With Hyper- Threading Technology......Page 257
7.6.10. Identifying Logical Processors in an MP System......Page 258
7.6.11.1. Use the PAUSE Instruction in Spin-Wait Loops......Page 264
7.6.11.4. Eliminate Execution-Based Timing Loops......Page 265
7.6.11.5. Place Locks and Semaphores in Aligned, 128-Byte Blocks of Memory......Page 266
8.1. Local and I/O APIC Overview......Page 269
8.3. Relationship Between the Intel 82489DX External APIC, the APIC, and the xAPIC......Page 273
8.4.1. The Local APIC Block Diagram......Page 274
8.4.2. Presence of the Local APIC......Page 277
8.4.3. Enabling or Disabling the Local APIC......Page 278
8.4.6. Local APIC ID......Page 279
8.4.7.1. Local APIC State After Power-Up or Reset......Page 280
8.4.7.3. Local APIC State After an INIT Reset (“Wait-for-SIPI” State)......Page 281
8.4.8. Local APIC Version Register......Page 282
8.5.1. Local Vector Table......Page 283
8.5.3. Error Handling......Page 286
8.5.4. APIC Timer......Page 288
8.6.1. Interrupt Command Register (ICR)......Page 289
8.6.2.1. Physical Destination Mode......Page 295
8.6.2.2. Logical Destination Mode......Page 296
8.6.2.4. Lowest Priority Delivery Mode......Page 297
8.8. Handling Interrupts......Page 299
8.8.2. Interrupt Handling with the P6 Family and Pentium Processors......Page 300
8.8.3. Interrupt, Task, and Processor Priority......Page 302
8.8.3.1. Task and Processor Priorities......Page 303
8.8.4. Interrupt Acceptance for Fixed Interrupts......Page 304
8.8.5. Signaling Interrupt Servicing Completion......Page 305
8.9. Spurious Interrupt......Page 306
8.10. APIC Bus Message Passing Mechanism and Protocol (P6 Family and Pentium Processors Only)......Page 307
8.10.1. Bus Message Formats......Page 308
9.1. Initialization Overview......Page 311
9.1.2. Processor Built-In Self-Test (BIST)......Page 312
9.1.3. Model and Stepping Information......Page 315
9.2.1. Configuring the x87 FPU Environment......Page 316
9.2.2. Setting the Processor for x87 FPU Software Emulation......Page 317
9.4. Model-Specific Registers (MSRs)......Page 318
9.6. SSE and SSE2 Extensions Initialization......Page 319
9.7.2. NMI Interrupt Handling......Page 320
9.8. Software Initialization for Protected-Mode Operation......Page 321
9.8.3. Initializing Paging......Page 322
9.9. Mode Switching......Page 323
9.9.1. Switching to Protected Mode......Page 324
9.9.2. Switching Back to Real-Address Mode......Page 325
9.10. Initialization and Mode Switching Example......Page 326
9.10.1. Assembler Usage......Page 328
9.10.2. STARTUP.ASM Listing......Page 329
9.10.3. MAIN.ASM Source Code......Page 338
9.10.4. Supporting Files......Page 339
9.11.1. Microcode Update......Page 341
9.11.2. Microcode Update Loader......Page 344
9.11.2.1. Update Loading Procedure......Page 345
9.11.3. Update Signature and Verification......Page 346
9.11.3.2. Authenticating the Update......Page 347
9.11.4.1. Responsibilities of the BIOS......Page 348
9.11.4.2. Responsibilities of the Calling Program......Page 349
9.11.4.4. INT 15H-based Interface......Page 352
9.11.4.6. Function 01H—Write Microcode Update Data......Page 353
9.11.4.7. Function 02H—Microcode Update Control......Page 357
9.11.4.8. Function 03H—Read Microcode Update Data......Page 358
9.11.4.9. Return Codes......Page 359
10.1. Internal Caches, TLBs, and Buffers......Page 363
10.2. Caching Terminology......Page 366
10.3. Methods of Caching Available......Page 367
10.3.1. Buffering of Write Combining Memory Locations......Page 369
10.3.2. Choosing a Memory Type......Page 370
10.4. Cache Control Protocol......Page 371
10.5.1. Cache Control Registers and Bits......Page 372
10.5.2. Precedence of Cache Controls......Page 376
10.5.2.1. Selecting Memory Types for Pentium Pro and Pentium II Processors......Page 377
10.5.2.2. Selecting Memory Types for Pentium 4, Intel Xeon, and Pentium III Processors......Page 378
10.5.3. Preventing Caching......Page 379
10.5.5. Cache Management Instructions......Page 380
10.6. Self-Modifying Code......Page 381
10.8. Explicit Caching......Page 382
10.9. Invalidating the Translation Lookaside Buffers (TLBs)......Page 383
10.11. Memory Type Range Registers (MTRRs)......Page 384
10.11.1. MTRR Feature Identification......Page 386
10.11.2.1. IA32_MTRR_DEF_TYPE MSR......Page 387
10.11.2.2. Fixed Range MTRRs......Page 388
10.11.2.3. Variable Range MTRRs......Page 389
10.11.3. Example Base and Mask Calculations......Page 391
10.11.4. Range Size and Alignment Requirement......Page 392
10.11.6. Remapping Memory Types......Page 393
10.11.7.1. MemTypeGet() Function......Page 394
10.11.7.2. MemTypeSet() Function......Page 396
10.11.8. MTRR Considerations in MP Systems......Page 397
10.12. Page Attribute Table (PAT)......Page 399
10.12.2. IA32_CR_PAT MSR......Page 400
10.12.3. Selecting a Memory Type from the PAT......Page 401
10.12.4. Programming the PAT......Page 402
10.12.5. PAT Compatibility with Earlier IA-32 Processors......Page 403
11.2. The MMX State and MMX Register Aliasing......Page 407
11.2.1. Effect of MMX, x87 FPU, FXSAVE, and FXRSTOR Instructions on the x87 FPU Tag Word......Page 409
11.3. Saving and Restoring the MMX State and Registers......Page 410
11.5. EXCEPTIONS That Can Occur When Executing MMX Instructions......Page 411
11.6. Debugging MMX Code......Page 412
12.1.1. General Guidelines for Adding Support to an Operating System for the SSE and SSE2 Extensions......Page 417
12.1.4. Initialization of the SSE and SSE2 Extensions......Page 418
12.1.5. Providing Non-Numeric Exception Handlers for Exceptions Generated by the SSE and SSE2 Ins.........Page 419
12.1.6. Providing an Handler for the SIMD Floating-Point Exception (#XF)......Page 421
12.3. Saving and Restoring the SSE and SSE2 State......Page 422
12.5. Designing Operating System Facilities for Automatically Saving x87 FPU, MMX, SSE, and SSE2 .........Page 423
12.5.1. Using the TS Flag to Control the Saving of the x87 FPU, MMX, SSE, and SSE2 State......Page 424
13.1. System Management Mode Overview......Page 429
13.3. Switching Between SMM and the Other Processor Operating Modes......Page 430
13.3.2. Exiting From SMM......Page 431
13.4. SMRAM......Page 432
13.4.1. SMRAM State Save Map......Page 433
13.4.2. SMRAM Caching......Page 436
13.5. SMI Handler Execution Environment......Page 437
13.6. Exceptions and Interrupts Within SMM......Page 438
13.8. Saving the x87 FPU State While in SMM......Page 440
13.9. SMM Revision Identifier......Page 441
13.10. Auto HALT Restart......Page 442
13.11.1. Relocating SMRAM to an Address Above 1 MByte......Page 443
13.12. I/O Instruction Restart......Page 444
13.13. SMM Multiple-Processor Considerations......Page 445
13.14. Thermal Monitoring......Page 446
13.14.2. Automatic Thermal Monitor......Page 447
13.14.3. Software Controlled Clock Modulation......Page 449
13.14.5. Usage Models for the Thermal Monitor and Software Controlled Clock Modulation......Page 450
13.14.6. Detection and Measurement of Over-Temperature Conditions......Page 451
14.2. Compatibility with Pentium Processor......Page 455
14.3.1.1. IA32_MCG_CAP MSR (Pentium 4 and Intel Xeon Processors)......Page 456
14.3.1.2. MCG_CAP MSR (P6 Family Processors)......Page 457
14.3.1.3. IA32_MCG_STATUS MSR......Page 458
14.3.2.1. IA32_MCi_CTL MSRs......Page 459
14.3.2.2. IA32_MCi_STATUS MSRs......Page 460
14.3.2.3. IA32_MCi_ADDR MSRs......Page 461
14.3.2.5. IA32_MCG Extended Machine Check State MSRs......Page 462
14.3.3. Mapping of the Pentium Processor Machine-Check Errors to the Machine-Check Architecture......Page 463
14.5. Machine-Check Initialization......Page 464
14.6.1. Simple Error Codes......Page 465
14.6.2. Compound Error Codes......Page 466
14.7. Guidelines for Writing Machine-Check Software......Page 468
14.7.1. Machine-Check Exception Handler......Page 469
14.7.3. Logging Correctable Machine-Check Errors......Page 471
15.1. Overview of the Debugging Support Facilities......Page 477
15.2. Debug Registers......Page 478
15.2.1. Debug Address Registers (DR0-DR3)......Page 479
15.2.4. Debug Control Register (DR7)......Page 480
15.3. Debug Exceptions......Page 482
15.3.1.1. Instruction-Breakpoint Exception Condition......Page 483
15.3.1.3. General-Detect Exception Condition......Page 485
15.3.2. Breakpoint Exception (#BP)—Interrupt Vector 3......Page 486
15.5. Last Branch, Interrupt, and Exception Recording (Pentium 4 and Intel Xeon Processors)......Page 487
15.5.1. IA32_DEBUGCTL MSR (Pentium 4 and Intel Xeon Processors)......Page 488
15.5.2. LBR Stack (Pentium 4 and Intel Xeon Processors)......Page 489
15.5.5. Branch Trace Messages......Page 491
15.5.7.1. Detection of the BTS Facilities......Page 492
15.5.7.2. Setting Up the DS Save Area......Page 493
15.5.7.4. Writing the DS Interrupt Service Routine......Page 494
15.6.1. DebugCtlMSR Register (P6 Family Processors)......Page 495
15.6.3. Monitoring Branches, Exceptions, and Interrupts (P6 Family Processors)......Page 497
15.7. Time-Stamp Counter......Page 498
15.9. Performance Monitoring (Pentium 4 and Intel Xeon Processors)......Page 499
15.9.1. ESCR MSRs......Page 503
15.9.2. Performance Counters......Page 505
15.9.3. CCCR MSRs......Page 506
15.9.5. DS Save Area......Page 509
15.9.6. Programming the Performance Counters for Non- Retirement Events......Page 512
15.9.6.1. Selecting Events to Count......Page 513
15.9.6.2. Filtering Events......Page 516
15.9.6.3. Starting Event Counting......Page 517
15.9.6.6. Cascading Counters......Page 518
15.9.6.7. Generating an Interrupt on Overflow......Page 519
15.9.7. At-Retirement Counting......Page 520
15.9.7.1. Using At-Retirement Counting......Page 521
15.9.7.3. Tagging Mechanism For Execution_event......Page 522
15.9.8. Precise Event-Based Sampling (PEBS)......Page 523
15.9.8.3. Setting Up the PEBS Buffer......Page 524
15.9.9. Counting Clocks......Page 525
15.10. Performance Monitoring and Hyper-Threading Technology......Page 527
15.10.1. ESCR MSRs......Page 528
15.10.2. CCCR MSRs......Page 529
15.10.3. IA32_PEBS_ENABLE MSR......Page 531
15.10.4. Performance Monitoring Events......Page 532
15.11. performance Monitoring (P6 Family Processor)......Page 533
15.11.1. PerfEvtSel0 and PerfEvtSel1 MSRs......Page 534
15.11.2. PerfCtr0 and PerfCtr1 MSRs......Page 536
15.11.4. Event and Time-Stamp Monitoring Software......Page 537
15.12. Performance Monitoring (Pentium Processors)......Page 538
15.12.1. Control and Event Select Register (CESR)......Page 539
15.12.2. Use of the Performance-Monitoring Pins......Page 540
15.12.3. Events Counted......Page 541
16.1. Real-Address Mode......Page 545
16.1.1. Address Translation in Real-Address Mode......Page 547
16.1.3. Instructions Supported in Real-Address Mode......Page 548
16.1.4. Interrupt and Exception Handling......Page 550
16.2. Virtual-8086 Mode......Page 551
16.2.1. Enabling Virtual-8086 Mode......Page 552
16.2.2. Structure of a Virtual-8086 Task......Page 553
16.2.3. Paging of Virtual-8086 Tasks......Page 554
16.2.5. Entering Virtual-8086 Mode......Page 555
16.2.6. Leaving Virtual-8086 Mode......Page 556
16.2.8.1. I/O-Port-Mapped I/O......Page 558
16.3. Interrupt and Exception Handling in Virtual-8086 Mode......Page 559
16.3.1.1. Handling an Interrupt or Exception Through a Protected-Mode Trap or Interrupt Gate......Page 561
16.3.1.2. Handling an Interrupt or Exception With an 8086 Program Interrupt or Exception Handler......Page 563
16.3.2. Class 2—Maskable Hardware Interrupt Handling in Virtual- 8086 Mode Using the Virtual Inte.........Page 564
16.3.3. Class 3—Software Interrupt Handling in Virtual-8086 Mode......Page 567
16.3.3.1. Method 1: Software Interrupt Handling......Page 569
16.3.3.4. Method 5: Software Interrupt Handling......Page 570
16.3.3.5. Method 6: Software Interrupt Handling......Page 571
16.4. Protected-Mode Virtual Interrupts......Page 572
CHAPTER 17 Mixing 16-Bit and 32-Bit Code......Page 575
17.2. Mixing 16-Bit and 32-Bit Operations Within a Code Segment......Page 576
17.3. Sharing Data Among Mixed-Size Code Segments......Page 577
17.4. Transferring Control Among Mixed-Size Code Segments......Page 578
17.4.2. Stack Management for Control Transfer......Page 579
17.4.2.2. Passing Parameters With a Gate......Page 581
17.4.5. Writing Interface Procedures......Page 582
18.2. Reserved Bits......Page 587
18.4. Detecting the Presence of New Features Through Software......Page 588
18.8. Hyper-Threading Technology......Page 589
18.9.1. Instructions Added Prior to the Pentium Processor......Page 590
18.12. New Flags in the EFLAGS Register......Page 591
18.13.1. PUSH SP......Page 592
18.14.1. Control Register CR0 Flags......Page 593
18.14.2.1. Condition Code Flags (C0 through C3)......Page 594
18.14.4. x87 FPU Tag Word......Page 595
18.14.6. Floating-Point Exceptions......Page 596
18.14.6.3. Numeric Underflow Exception (#U)......Page 597
18.14.6.7. Assertion of the FERR# Pin......Page 598
18.14.6.12. Coprocessor Segment Overrun Exception......Page 599
18.14.7.2. FSCALE Instruction......Page 600
18.14.7.8. FSIN, FCOS, and FSINCOS Instructions......Page 601
18.14.7.13. Load Constant Instructions......Page 602
18.14.8. Transcendental Instructions......Page 603
18.15. Serializing Instructions......Page 604
18.16.2. Intel486 SX Processor and Intel487SX Math Coprocessor Initialization......Page 605
18.17. Control Registers......Page 606
18.18.1.2. Global Pages......Page 608
18.19. Debug Facilities......Page 609
18.20. Test Registers......Page 610
18.21. Exceptions and/or Exception Conditions......Page 611
18.21.2. Priority OF Exceptions......Page 612
18.23. Advanced Programmable Interrupt Controller (APIC)......Page 613
18.23.2. New Features Incorporated in the Local APIC for the P6 Family and Pentium Processors......Page 614
18.24.3. Order of Reads/Writes to the TSS......Page 615
18.24.5. Differences in I/O Map Base Addresses......Page 616
18.25. Cache Management......Page 617
18.25.1. Self-Modifying Code with Cache Enabled......Page 618
18.26.3. Enabling and Disabling Paging......Page 619
18.27.1. Selector Pushes and Pops......Page 620
18.28. Mixing 16- and 32-Bit Segments......Page 621
18.29.1. Segment Wraparound......Page 622
18.30. Store Buffers and Memory Ordering......Page 623
18.31. Bus Locking......Page 624
18.33.2. RDMSR and WRMSR Instructions......Page 625
18.33.4. Machine-Check Exception and Architecture......Page 626
18.34. Two Ways to Run Intel 286 Processor Tasks......Page 627
A.1. Pentium 4 and Intel Xeon Processor Performance-Monitoring Events......Page 631
A.2. P6 Family Processor Performance-Monitoring Events......Page 668
A.3. Pentium Processor Performance-Monitoring Events......Page 679
B.1. MSRs In the Pentium 4 and Intel Xeon Processors......Page 693
B.2. MSRs In the P6 Family Processors......Page 708
B.3. MSRs in Pentium Processors......Page 717
B.4. Architectural MSRs......Page 718
C.1. Overview of the MP Initialization Process For P6 Family Processors......Page 723
C.2. MP Initialization Protocol Algorithm......Page 724
C.2.1. Error Detection and Handling During the MP Initialization Protocol......Page 726
D.2. LINT[0:1] Pins Programming Procedure......Page 729
APPENDIX E Interpreting Machine-Check Error Codes......Page 733
F.2. EOI Message......Page 739
F.2.1. Short Message......Page 740
F.2.2. Non-focused Lowest Priority Message......Page 741
F.2.3. APIC Bus Status Cycles......Page 742
Index......Page 745