High Performance ASIC Design: Using Synthesizable Domino Logic in an ASIC Flow

HIGH PERFORMANCE ASIC DESIGN: USING SYNTHESIZABLE DOMINO LOGIC IN AN ASIC FLOW......Page 1
Half-title......Page 3
Title......Page 5
Copyright......Page 6
Contents......Page 7
Preface......Page 9
Abbreviations......Page 11
1.1 CMOS and NMOS......Page 13
1.2 Domino logic circuits......Page 17
1.3 Clocking domino logic......Page 24
1.4 Summary......Page 27
References......Page 28
2.1 Microprocessors since 1989......Page 30
2.2.1 Fast arithmetic modules......Page 34
2.2.2 Predictive logic and parallel computation......Page 37
2.2.3 Optimizing across logic and circuit design......Page 41
2.2.4 Remarks......Page 42
2.3 Designing and using high-speed memories......Page 43
References......Page 47
3.1 High-speed digital circuit design......Page 49
3.2 An introduction to standard cells......Page 54
3.3.1 Starting the design......Page 57
3.3.2 Choosing drive sizes......Page 58
3.4 Circuit design of domino logic cells: a qualitative approach......Page 60
3.4.1 Charge sharing......Page 61
3.4.2 Crosstalk noise......Page 62
3.5 Circuit design of domino logic cells: a quantitative approach......Page 63
3.5.1 Cell delay and output transition time measurement......Page 64
3.5.3 Setup measurement of data input rising relative to the clock falling......Page 66
3.5.4 Minimum pulse width high overlap characterization (MPWHO)......Page 67
3.5.5 Data pin hold falling measurement......Page 70
3.5.7 Minimum clock pulse width for low and high phases......Page 71
3.5.8 Data pin maximum noise spike characterization......Page 73
3.5.9 Charge-sharing check......Page 74
3.6 Characterizing domino logic-compatible registers......Page 75
3.6.1 Clock to output delay and transition characterization......Page 76
3.7 Layout of domino logic standard cells......Page 77
3.8 Timing models for domino logic cells......Page 78
References......Page 81
4.1 Introduction to domino logic synthesis......Page 82
4.1.1 A standard tool-based approach to domino logic synthesis......Page 83
4.2 Unate transform......Page 85
4.3 Phase assignment......Page 87
4.4 Phase-assignment rules......Page 89
4.4.1 Phase skipping in domino cells......Page 90
4.4.2 Unbalanced phase assignment......Page 91
4.4.3 Fan-in phase differences......Page 92
4.4.4 Static input ports......Page 93
4.4.5 Domino input ports......Page 94
4.4.8 Static output ports......Page 95
4.4.10 Multi cycle paths......Page 96
4.4.11 Phase assignment with static and domino cells......Page 97
4.5.1 Overview......Page 98
4.5.2 Domino flow-specific variables......Page 99
4.5.3 Design guidelines......Page 103
4.5.4 Constraint settings......Page 104
4.5.5  RTL description......Page 107
4.5.7 Bubble pushing......Page 108
4.5.8 Post-bubble pushing incremental optimization......Page 109
4.5.10 Phase-assignment variable options......Page 110
4.5.11 Phase assignment: detailed description......Page 113
4.5.13 Back end flow execution......Page 115
4.5.15 Crosstalk check......Page 116
4.5.17 Final comments......Page 117
4.6 Schematic capture of domino designs......Page 118
References......Page 119
5.2 Domino integer execution unit......Page 120
5.2.1 Dual-output domino logic......Page 121
5.2.2 Schematic capture and library specification......Page 123
5.2.3 Delay, power, and crosstalk analysis......Page 124
5.2.4 Transistor sizing guidelines......Page 125
5.2.5 Design of the execution unit......Page 127
5.2.6 Silicon results......Page 128
5.3 A synthesized domino logic DSP core......Page 131
5.4 A synthesizable domino logic Viterbi add–compare–select (ACS) test chip......Page 133
5.4.1 Silicon results......Page 135
5.5 Intel’s published domino logic synthesis flow......Page 136
References......Page 138
6.1 The state of digital ASIC design methodologies......Page 139
6.2 Process trends and domino logic......Page 140
6.3 Clocking methodology for domino circuits......Page 142
6.4.1 Non-footed domino logic......Page 144
6.4.3 Compound domino......Page 146
6.4.4 Other dynamic logic styles......Page 147
6.5 Flow improvements for domino synthesis......Page 149
6.5.1 Allowing binate logic in domino designs......Page 150
6.5.2 Clock modification to allow for the use of more non-footed domino......Page 152
6.6 The case for domino logic synthesis......Page 153
References......Page 154
Index......Page 155