Hardware virtualization on a coarse-grained reconfigurable processor

Contents......Page 8
1 Introduction......Page 16
1.1 Research Topics in Reconfigurable Architectures for Embedded Systems......Page 17
1.2 Contributions......Page 20
1.3 Application Specification and Execution on the Zippy Architecture......Page 22
1.4 Preliminary Work at ETH......Page 25
1.5 Thesis outline......Page 26
2 Dynamically Reconfigurable Processor Architecture......Page 28
2.1 Design Objectives......Page 29
2.2.1 Structure......Page 30
2.2.2 Embedded CPU core......Page 31
2.2.3 Reconfigurable Processing Unit......Page 32
2.3 Reconfigurable Processing Unit Architecture......Page 33
2.3.1 Reconfigurable Array......Page 34
2.3.2 FIFOs......Page 39
2.3.4 Context Sequencer and Synchronization......Page 41
2.3.5 Multi-Context Architecture......Page 45
2.3.7 Parameters of the Reconfigurable Processing Unit......Page 46
2.4 Summary......Page 47
3 Tool-Flow......Page 50
3.1 Tool-Flows for Coarse-Grained Reconfigurable Processors......Page 51
3.2 The Zippy Tool-Flow......Page 54
3.3.1 Hardware specification......Page 56
3.3.2 Architecture modeling......Page 58
3.3.3 Placement......Page 61
3.3.4 Routing......Page 64
3.3.5 Configuration Generation......Page 68
3.4.1 Hardware- Software Interface......Page 70
3.4.3 Extensions to the CPU Simulator......Page 71
3.4.4 Compilation Tool-Chain......Page 72
3.5 Summary......Page 73
4 Performance evaluation......Page 76
4.1.2 Challenges......Page 77
4.1.3 Approaches......Page 78
4.2 System-Level Cycle-Accurate Co-Simulation for Zippy......Page 79
4.2.2 CPU Simulation Model......Page 80
4.2.4 Cosimulation framework......Page 82
4.3 Summary......Page 86
5 Hardware Virtualization......Page 88
5.1.1 Hardware Virtualization Approaches......Page 89
5.1.2 Temporal Partitioning......Page 91
5.1.3 Virtualized Execution......Page 96
5.1.4 Virtual Machine......Page 99
5.2 Hardware Virtualization on the Zippy Architecture......Page 100
5.2.2 Virtualized Execution......Page 101
5.2.3 Temporal Partitioning......Page 102
5.3.1 Outline of the Method......Page 105
5.3.2 Models......Page 107
5.3.3 Basic Problem Formulation......Page 110
5.3.4 Resource Constraints......Page 113
5.3.7 Example......Page 120
5.3.8 Related Work and Discussion......Page 122
5.4 Summary......Page 125
6.1 Virtualized Execution of a Digital Filter......Page 126
6.1.1 FIR Filter Partitioning and Mapping......Page 127
6.1.2 Experimental Setup......Page 129
6.1.3 Results and Discussion......Page 130
6.2 Temporal Partitioning of an ADPCM Decoder......Page 133
6.2.2 Experiments......Page 134
6.2.3 Experimental Setup and Results......Page 137
6.3 Summary......Page 139
7.1 Contributions......Page 140
7.2 Conclusions......Page 142
7.3 Future Directions......Page 143
Bibliography......Page 146
A Acronyms......Page 156
B Curriculum Vitae......Page 158