Fundamentals of Modern VLSI Devices

Half title page......Page 2
Title page......Page 4
Copyright page......Page 5
Contents......Page 7
Preface to the first edition......Page 14
Preface to the second edition......Page 17
Physical constants and unit conversions......Page 19
List of symbols......Page 20
1.1.1 Historical Perspective......Page 28
1.1.2 Recent Developments......Page 31
1.2.1 Modern CMOS Transistors......Page 32
1.2.2 Modern Bipolar Transistors......Page 33
1.3 Scope and Brief Description of the Book......Page 35
2.1.1 Energy Bands in Silicon......Page 40
2.1.2 n-Type and p-Type Silicon......Page 48
2.1.3 Carrier Transport in Silicon......Page 54
2.1.4 Basic Equations for Device Operation......Page 60
2.2.1 Energy-Band Diagrams for a p–n Diode......Page 71
2.2.2 Abrupt Junctions......Page 74
2.2.3 The Diode Equation......Page 85
2.2.4 Current–Voltage Characteristics......Page 94
2.2.5 Time-Dependent and Switching Characteristics......Page 109
2.2.6 Diffusion Capacitance......Page 117
2.3 MOS Capacitors......Page 120
2.3.1 Surface Potential: Accumulation, Depletion, and Inversion......Page 121
2.3.2 Electrostatic Potential and Charge Distribution in Silicon......Page 129
2.3.3 Capacitances in an MOS Structure......Page 138
2.3.4 Polysilicon-Gate Work Function and Depletion Effects......Page 146
2.3.5 MOS under Nonequilibrium and Gated Diodes......Page 150
2.3.6 Charge in Silicon Dioxide and at the Silicon–Oxide Interface......Page 156
2.3.7 Effect of Interface Traps and Oxide Charge on Device Characteristics......Page 161
2.4 Metal–Silicon Contacts......Page 168
2.4.1 Static Characteristics of a Schottky Barrier Diode......Page 169
2.4.2 Current Transport in a Schottky Barrier Diode......Page 177
2.4.3 Current–Voltage Characteristics of a Schottky Barrier Diode......Page 178
2.4.4 Ohmic Contacts......Page 184
2.5.1 Impact Ionization and Avalanche Breakdown......Page 187
2.5.2 Band-to-Band Tunneling......Page 192
2.5.3 Tunneling into and through Silicon Dioxide......Page 193
2.5.4 Injection of Hot Carriers from Silicon into Silicon Dioxide......Page 201
2.5.5 High-Field Effects in Gated Diodes......Page 204
2.5.6 Dielectric Breakdown......Page 206
Exercises......Page 212
3 MOSFET Devices......Page 221
3.1 Long-Channel MOSFETs......Page 222
3.1.1 Drain-Current Model......Page 223
3.1.2 MOSFET I–V Characteristics......Page 230
3.1.3 Subthreshold Characteristics......Page 240
3.1.4 Substrate Bias and Temperature Dependence of Threshold Voltage......Page 244
3.1.5 MOSFET Channel Mobility......Page 248
3.1.6 MOSFET Capacitances and Inversion-Layer Capacitance Effect......Page 251
3.2 Short-Channel MOSFETs......Page 256
3.2.1 Short-Channel Effect......Page 257
3.2.2 Velocity Saturation and High-Field Transport......Page 271
3.2.3 Channel Length Modulation......Page 282
3.2.4 Source–Drain Series Resistance......Page 284
3.2.5 MOSFET Degradation and Breakdown at High Fields......Page 285
Exercises......Page 291
4.1.1 Constant-Field Scaling......Page 295
4.1.2 Generalized Scaling......Page 299
4.1.3 Nonscaling Effects......Page 303
4.2.1 Threshold-Voltage Requirement......Page 306
4.2.2 Channel Profile Design......Page 312
4.2.3 Nonuniform Doping......Page 321
4.2.4 Quantum Effect on Threshold Voltage......Page 334
4.2.5 Discrete Dopant Effects on Threshold Voltage......Page 341
4.3.1 Various Definitions of Channel Length......Page 344
4.3.2 Extraction of the Effective Channel Length......Page 346
4.3.3 Physical Meaning of Effective Channel Length......Page 352
4.3.4 Extraction of Channel Length by C–V Measurements......Page 358
Exercises......Page 360
5.1 Basic CMOS Circuit Elements......Page 365
5.1.1 CMOS Inverters......Page 366
5.1.2 CMOS NAND and NOR Gates......Page 378
5.1.3 Inverter and NAND Layouts......Page 384
5.2.1 Source–Drain Resistance......Page 387
5.2.2 Parasitic Capacitances......Page 392
5.2.3 Gate Resistance......Page 396
5.2.4 Interconnect R and C......Page 399
5.3.1 Propagation Delay and Delay Equation......Page 407
5.3.2 Delay Sensitivity to Channel Width, Length, and Gate Oxide Thickness......Page 416
5.3.3 Sensitivity of Delay to Power-Supply Voltage and Threshold Voltage......Page 420
5.3.4 Sensitivity of Delay to Parasitic Resistance and Capacitance......Page 422
5.3.5 Delay of Two-Way NAND and Body Effect......Page 426
5.4 Performance Factors of Advanced CMOS Devices......Page 430
5.4.1 MOSFETs in RF Circuits......Page 431
5.4.2 Effect of Transport Parameters on CMOS Performance......Page 435
5.4.3 Low-Temperature CMOS......Page 437
Exercises......Page 440
6.1 n–p–n Transistors......Page 444
6.1.2 Modifying the Simple Diode Theory for Describing Bipolar Transistors......Page 449
6.2 Ideal Current–Voltage Characteristics......Page 456
6.2.1 Collector Current......Page 458
6.2.2 Base Current......Page 461
6.2.3 Current Gains......Page 466
6.2.4 Ideal IC–VCE Characteristics......Page 468
6.3 Characteristics of a Typical n–p–n Transistor......Page 470
6.3.1 Effect of Emitter and Base Series Resistances......Page 471
6.3.2 Effect of Base–Collector Voltage on Collector Current......Page 473
6.3.3 Collector Current Falloff at High Currents......Page 479
6.3.4 Nonideal Base Current at Low Currents......Page 486
6.4.1 Basic dc Model......Page 489
6.4.2 Basic ac Model......Page 493
6.4.3 Small-Signal Equivalent-Circuit Model......Page 495
6.4.4 Emitter Diffusion Capacitance......Page 498
6.4.5 Charge-Control Analysis......Page 501
6.5 Breakdown Voltages......Page 507
6.5.1 Common-Base Current Gain in the Presence of Base–Collector Junction Avalanche......Page 508
6.5.2 Saturation Currents in a Transistor......Page 511
6.5.3 Relation Between BVCEO and BVCBO......Page 512
Exercises......Page 514
7.1 Design of the Emitter Region......Page 518
7.1.1 Diffused or Implanted-and-Diffused Emitter......Page 519
7.1.2 Polysilicon Emitter......Page 520
7.2 Design of the Base Region......Page 522
7.2.1 Relationship between Base Sheet Resistivity and Collector Current Density......Page 524
7.2.2 Intrinsic-Base Dopant Distribution......Page 525
7.2.3 Electric Field in the Quasineutral Intrinsic Base......Page 527
7.2.4 Base Transit Time......Page 531
7.3 Design of the Collector Region......Page 533
7.3.1 Collector Design When There Is Negligible Base Widening......Page 535
7.3.2 Collector Design When There Is Appreciable Base Widening......Page 537
7.4 SiGe-Base Bipolar Transistors......Page 538
7.4.1 Transistors Having a Simple Linearly Graded Base Bandgap......Page 540
7.4.2 Base Current When Ge Is Present in the Emitter......Page 547
7.4.3 Transistors Having a Trapezoidal Ge Distribution in the Base......Page 554
7.4.4 Transistors Having a Constant Ge Distribution in the Base......Page 559
7.4.5 Effect of Emitter Depth Variation on Device Characteristics......Page 564
7.4.6 Some Optimal Ge Profiles......Page 569
7.4.7 Base-Width Modulation by VBE......Page 576
7.4.8 Reverse–Mode I–V Characteristics......Page 582
7.4.9 Heterojunction Nature of a SiGe-Base Bipolar Transistor......Page 585
7.5 Modern Bipolar Transistor Structures......Page 589
7.5.1 Deep-Trench Isolation......Page 590
7.5.3 Self-Aligned Polysilicon Base Contact......Page 591
7.5.5 SiGe-Base......Page 592
Exercises......Page 593
8.1.1 Cutoff Frequency......Page 599
8.1.3 Ring Oscillator and Gate Delay......Page 603
8.2 Digital Bipolar Circuits......Page 604
8.2.1 Delay Components of a Logic Gate......Page 606
8.2.2 Device Structure and Layout for Digital Circuits......Page 610
8.3.1 Design Points for a Digital Circuit......Page 612
8.3.2 Device Optimization When There Is Significant Base Widening......Page 614
8.3.3 Device Optimization When There Is Negligible Base Widening......Page 615
8.3.4 Device Optimization for Small Power–Delay Product......Page 620
8.3.5 Bipolar Device Optimization from Some Data Analyses......Page 622
8.4 Bipolar Device Scaling for ECL Circuits......Page 625
8.4.1 Device Scaling Rules......Page 627
8.4.2 Limits in Bipolar Device Scaling for ECL Circuits......Page 629
8.5 Bipolar Device Optimization and Scaling for RF and Analog Circuits......Page 632
8.5.1 The Single-Transistor Amplifier......Page 633
8.5.2 Optimizing the Individual Parameters......Page 634
8.5.3 Technology for RF and Analog Bipolar Devices......Page 638
8.6 Comparing a SiGe-Base Bipolar Transistor with a GaAs HBT......Page 640
Exercises......Page 644
9 Memory Devices......Page 650
9.1.1 CMOS SRAM Cell......Page 652
9.1.2 Other Bistable MOSFET SRAM Cells......Page 663
9.1.3 Bipolar SRAM Cell......Page 664
9.2.1 Basic DRAM Cell and Its Operation......Page 675
9.2.2 Device Design and Scaling Considerations for a DRAM Cell......Page 680
9.3 Nonvolatile Memory......Page 681
9.3.1 MOSFET Nonvolatile Memory Devices......Page 682
9.3.2 Flash Memory Arrays......Page 690
9.3.3 Floating-Gate Nonvolatile Memory Cells......Page 694
9.3.4 Nonvolatile Memory Cells with Charge Stored in Insulator......Page 697
Exercise......Page 700
10.1 SOI CMOS......Page 702
10.1.1 Partially Depleted SOI MOSFETs......Page 704
10.1.2 Fully Depleted SOI MOSFETs......Page 705
10.2 Thin-Silicon SOI Bipolar......Page 709
10.2.1 Fully Depleted Collector Mode......Page 712
10.2.2 Partially Depleted Collector Mode......Page 714
10.2.3 Accumulation Collector Mode......Page 715
10.2.4 Discussion......Page 716
10.3 Double-Gate MOSFETs......Page 717
10.3.1 An Analytic Drain Current Model for Symmetric DG MOSFETs......Page 718
10.3.2 The Scale Length of Double-Gate MOSFETs......Page 723
10.3.3 Fabrication Requirements and Challenges of DG MOSFETs......Page 724
10.3.4 Multiple-Gate MOSFETs......Page 726
Exercise......Page 728
Appendix 1 CMOS Process Flow......Page 729
Appendix 2 Outline of a Process for Fabricating Modern n–p–n Bipolar Transistors......Page 733
Appendix 3 Einstein Relations......Page 734
Appendix 4 Spatial Variation of Quasi-Fermi Potentials......Page 738
Appendix 5 Generation and Recombination Processes and Space-Charge-Region Current......Page 747
Appendix 6 Diffusion Capacitance of a p–n Diode......Page 759
Appendix 7 Image-Force-Induced Barrier Lowering......Page 768
Appendix 8 Electron-Initiated and Hole-Initiated Avalanche Breakdown......Page 773
Appendix 9 An Analytical Solution for the Short-Channel Effect in Subthreshold......Page 775
Appendix 10 Generalized MOSFET Scale Length Model......Page 785
Appendix 11 Drain Current Model of a Ballistic MOSFET......Page 793
Appendix 12 Quantum-Mechanical Solution in Weak Inversion......Page 801
Appendix 13 Power Gain of a Two-Port Network......Page 806
Appendix 14 Unity-Gain Frequencies of a MOSFET Transistor......Page 809
Appendix 15 Determination of Emitter and Base Series Resistances......Page 814
Appendix 16 Intrinsic-Base Resistance......Page 819
Appendix 17 Energy-Band Diagram of a Si–SiGe n–p Diode......Page 824
Appendix 18 fT and fmax of a Bipolar Transistor......Page 828
References......Page 835
Index......Page 872