Fundamentals of logic design

Front Cover......Page 1
Title Page......Page 4
Copyright......Page 5
Contents......Page 8
Preface......Page 16
How to Use This Book for Self-Study......Page 20
Objectives......Page 24
Study Guide......Page 25
1.1 Digital Systems and Switching Circuits......Page 29
1.2 Number Systems and Conversion......Page 31
1.3 Binary Arithmetic......Page 35
1.4 Representation of Negative Numbers......Page 39
Addition of 2's Complement Numbers......Page 40
Addition of 1's Complement Numbers......Page 42
1.5 Binary Codes......Page 44
Problems......Page 46
Objectives......Page 50
Study Guide......Page 51
2.1 Introduction......Page 57
2.2 Basic Operations......Page 58
2.3 Boolean Expressions and Truth Tables......Page 60
2.4 Basic Theorems......Page 62
2.5 Commutative, Associative, and Distributive Laws......Page 63
2.6 Simplification Theorems......Page 65
2.7 Multiplying Out and Factoring......Page 67
2.8 DeMorgan's Laws......Page 70
Problems......Page 71
Laws and Theorems of Boolean Algebra......Page 78
Objectives......Page 79
Study Guide......Page 80
3.1 Multiplying Out and Factoring Expressions......Page 85
3.2 Exclusive-OR and Equivalence Operations......Page 87
3.3 The Consensus Theorem......Page 89
3.4 Algebraic Simplification of Switching Expressions......Page 91
3.5 Proving Validity of an Equation......Page 93
Programmed Exercises......Page 96
Problems......Page 101
Objectives......Page 106
Study Guide......Page 107
4.1 Conversion of English Sentences to Boolean Equations......Page 113
4.2 Combinational Logic Design Using a Truth Table......Page 115
4.3 Minterm and Maxterm Expansions......Page 116
4.4 General Minterm and Maxterm Expansions......Page 119
4.5 Incompletely Specified Functions......Page 122
4.6 Examples of Truth Table Construction......Page 123
4.7 Design of Binary Adders and Subtracters......Page 127
Problems......Page 130
Objectives......Page 139
Study Guide......Page 140
5.1 Minimum Forms of Switching Functions......Page 150
5.2 Two- and Three-Variable Karnaugh Maps......Page 152
5.3 Four-Variable Karnaugh Maps......Page 156
5.4 Determination of Minimum Expressions Using Essential Prime Implicants......Page 159
5.5 Five-Variable Karnaugh Maps......Page 164
5.6 Other Uses of Karnaugh Maps......Page 167
5.7 Other Forms of Karnaugh Maps......Page 169
Programmed Exercises......Page 170
Problems......Page 175
Objectives......Page 182
Study Guide......Page 183
6.1 Determination of Prime Implicants......Page 188
6.2 The Prime Implicant Chart......Page 191
6.3 Petrick's Method......Page 194
6.4 Simplification of Incompletely Specified Functions......Page 196
6.5 Simplification Using Map-Entered Variables......Page 197
6.6 Conclusion......Page 199
Programmed Exercise......Page 200
Problems......Page 204
Objectives......Page 207
Study Guide......Page 208
7.1 Multi-Level Gate Circuits......Page 213
7.2 NAND and NOR Gates......Page 218
7.3 Design of Two-Level NAND- and NOR- Gate Circuits......Page 220
7.4 Design of Multi-Level NAND- and NOR- Gate Circuits......Page 223
7.5 Circuit Conversion Using Alternative Gate Symbols......Page 224
7.6 Design of Two-Level, Multiple-Output Circuits......Page 227
Determination of Essential Prime Implicants for Multiple-Output Realization......Page 229
Problems......Page 231
Objectives......Page 238
Study Guide......Page 239
8.1 Review of Combinational Circuit Design......Page 242
8.2 Design of Circuits with Limited Gate Fan-In......Page 243
8.3 Gate Delays and Timing Diagrams......Page 245
8.4 Hazards in Combinational Logic......Page 247
8.5 Simulation and Testing of Logic Circuits......Page 252
Problems......Page 255
Design Problems......Page 259
Objectives......Page 265
Study Guide......Page 266
9.1 Introduction......Page 273
9.2 Multiplexers......Page 274
9.3 Three-State Buffers......Page 276
9.4 Decoders and Encoders......Page 279
9.5 Read-Only Memories......Page 282
Programmable Logic Arrays......Page 286
Programmable Array Logic......Page 289
9.7 Complex Programmable Logic Devices......Page 291
9.8 Field-Programmable Gate Arrays......Page 293
Decomposition of Switching Functions......Page 294
Problems......Page 297
Objectives......Page 303
Study Guide......Page 304
10.1 VHDL Description of Combinational Circuits......Page 308
10.2 VHDL Models for Multiplexers......Page 313
10.3 VHDL Modules......Page 315
Four-Bit Full Adder......Page 317
10.4 Signals and Constants......Page 320
10.5 Arrays......Page 321
10.6 VHDL Operators......Page 324
10.7 Packages and Libraries......Page 325
10.8 IEEE Standard Logic......Page 327
10.9 Compilation and Simulation of VHDL Code......Page 330
Problems......Page 331
Design Problems......Page 336
Objectives......Page 340
Study Guide......Page 341
11.1 Introduction......Page 345
11.2 Set-Reset Latch......Page 346
11.3 Gated D Latch......Page 350
11.4 Edge-Triggered D Flip-Flop......Page 351
11.5 S-R Flip-Flop......Page 354
11.6 J-K Flip-Flop......Page 355
11.7 T Flip-Flop......Page 356
11.8 Flip-Flops with Additional Inputs......Page 357
11.9 Summary......Page 359
Problems......Page 360
Programmed Exercise......Page 368
Objectives......Page 371
Study Guide......Page 372
12.1 Registers and Register Transfers......Page 377
Parallel Adder with Accumulator......Page 379
12.2 Shift Registers......Page 381
12.3 Design of Binary Counters......Page 385
12.4 Counters for Other Sequences......Page 390
Counter Design Using D Flip-Flops......Page 393
12.5 Counter Design Using S-R and J-K Flip-Flops......Page 394
12.6 Derivation of Flip-Flop Input Equations—Summary......Page 397
Problems......Page 401
Objectives......Page 411
Study Guide......Page 412
13.1 A Sequential Parity Checker......Page 418
13.2 Analysis by Signal Tracing and Timing Charts......Page 420
13.3 State Tables and Graphs......Page 424
Construction and Interpretation of Timing Charts......Page 429
13.4 General Models for Sequential Circuits......Page 431
Programmed Exercise......Page 435
Problems......Page 439
Objectives......Page 450
Study Guide......Page 451
14.1 Design of a Sequence Detector......Page 454
14.2 More Complex Design Problems......Page 458
14.3 Guidelines for Construction of State Graphs......Page 462
14.4 Serial Data Code Conversion......Page 467
14.5 Alphanumeric State Graph Notation......Page 471
Programmed Exercises......Page 472
Problems......Page 479
Objectives......Page 489
Study Guide......Page 490
15.1 Elimination of Redundant States......Page 497
15.2 Equivalent States......Page 499
15.3 Determination of State Equivalence Using an Implication Table......Page 501
15.4 Equivalent Sequential Circuits......Page 504
15.5 Incompletely Specified State Tables......Page 506
15.6 Derivation of Flip-Flop Input Equations......Page 507
15.7 Equivalent State Assignments......Page 510
15.8 Guidelines for State Assignment......Page 513
15.9 Using a One-Hot State Assignment......Page 518
Problems......Page 521
Study Guide......Page 534
16.1 Summary of Design Procedure for Sequential Circuits......Page 537
16.2 Design Example—Code Converter......Page 538
Design of a Comparator......Page 542
16.4 Design of Sequential Circuits Using ROMs and PLAs......Page 545
16.5 Sequential Circuit Design Using CPLDs......Page 548
16.6 Sequential Circuit Design Using FPGAs......Page 552
16.7 Simulation and Testing of Sequential Circuits......Page 554
16.8 Overview of Computer-Aided Design......Page 559
Design Problems......Page 561
Additional Problems......Page 567
Objectives......Page 572
Study Guide......Page 573
17.1 Modeling Flip-Flops Using VHDL Processes......Page 577
17.2 Modeling Registers and Counters Using VHDL Processes......Page 581
17.3 Modeling Combinational Logic Using VHDL Processes......Page 586
17.4 Modeling a Sequential Machine......Page 588
17.5 Synthesis of VHDL Code......Page 595
17.6 More About Processes and Sequential Statements......Page 598
Problems......Page 600
Simulation Problems......Page 611
Objectives......Page 614
Study Guide......Page 615
18.1 Serial Adder with Accumulator......Page 617
18.2 Design of a Parallel Multiplier......Page 621
18.3 Design of a Binary Divider......Page 625
Programmed Exercises......Page 633
Problems......Page 635
Objectives......Page 646
Study Guide......Page 647
19.1 State Machine Charts......Page 648
19.2 Derivation of SM Charts......Page 653
19.3 Realization of SM Charts......Page 658
Problems......Page 663
Objectives......Page 669
Study Guide......Page 670
20.1 VHDL Code for a Serial Adder......Page 673
20.2 VHDL Code for a Binary Multiplier......Page 675
20.3 VHDL Code for a Binary Divider......Page 685
20.4 VHDL Code for a Dice Game Simulator......Page 687
20.5 Concluding Remarks......Page 690
Problems......Page 691
Lab Design Problems......Page 694
A MOS and CMOS Logic......Page 698
B VHDL Language Summary......Page 704
C Tips for Writing Synthesizable VHDL Code......Page 709
D Proofs of Theorems......Page 712
E Answers to Selected Study Guide Questions and Problems......Page 714
References......Page 770
Index......Page 771