Fundamentals of digital logic with VHDL design

Cover Page
Title Page
Copyright Page
Dedication
About the Authors
Preface
Acknowledgments
Contents
chapter 1: DESIGN CONCEPTS
	1.1 Digital Hardware
		1.1.1 Standard Chips
		1.1.2 Programmable Logic Devices
		1.1.3 Custom-Designed Chips
	1.2 The Design Process
	1.3 Design of Digital Hardware
		1.3.1 Basic Design Loop
		1.3.2 Structure of a Computer
		1.3.3 Design of a Digital Hardware Unit
	1.4 Logic Circuit Design in This Book
	1.5 Theory and Practice
	1.6 Binary Numbers
		1.6.1 Conversion between Decimal and Binary Systems
	References
chapter 2: INTRODUCTION TO LOGIC CIRCUITS
	2.1 Variables and Functions
	2.2 Inversion
	2.3 Truth Tables
	2.4 Logic Gates and Networks
		2.4.1 Analysis of a Logic Network
	2.5 Boolean Algebra
		2.5.1 The Venn Diagram
		2.5.2 Notation and Terminology
		2.5.3 Precedence of Operations
	2.6 Synthesis Using AND, OR, and NOT Gates
		2.6.1 Sum-of-Products and Product-of-Sums Forms
	2.7 NAND and NOR Logic Networks
	2.8 Design Examples
		2.8.1 Three-Way Light Control
		2.8.2 Multiplexer Circuit
	2.9 Introduction to CAD Tools
		2.9.1 Design Entry
		2.9.2 Synthesis
		2.9.3 Functional Simulation
		2.9.4 Physical Design
		2.9.5 Timing Simulation
		2.9.6 Chip Configuration
	2.10 Introduction to VHDL
		2.10.1 Representation of Digital Signals in VHDL
		2.10.2 Writing Simple VHDL Code
		2.10.3 How NOT to Write VHDL Code
	2.11 Concluding Remarks
	2.12 Examples of Solved Problems
	Problems
	References
chapter 3: IMPLEMENTATION TECHNOLOGY
	3.1 Transistor Switches
	3.2 NMOS Logic Gates
	3.3 CMOS Logic Gates
		3.3.1 Speed of Logic Gate Circuits
	3.4 Negative Logic System
	3.5 Standard Chips
		3.5.1 7400-Series Standard Chips
	3.6 Programmable Logic Devices
		3.6.1 Programmable Logic Array (PLA)
		3.6.2 Programmable Array Logic (PAL)
		3.6.3 Programming of PLAs and PALs
		3.6.4 Complex Programmable Logic Devices (CPLDs)
		3.6.5 Field-Programmable Gate Arrays
		3.6.6 Using CAD Tools to Implement Circuits in CPLDs and  FPGAs
		3.6.7 Applications of CPLDs and FPGAs
	3.7 Custom Chips, Standard Cells, and Gate Arrays
	3.8 Practical Aspects
		3.8.1 MOSFET Fabrication and Behavior
		3.8.2 MOSFET On-Resistance
		3.8.3 Voltage Levels in Logic Gates
		3.8.4 Noise Margin
		3.8.5 Dynamic Operation of Logic Gates
		3.8.6 Power Dissipation in Logic Gates
		3.8.7 Passing 1s and 0s Through Transistor Switches
		3.8.8 Fan-in and Fan-out in Logic Gates
	3.9 Transmission Gates
		3.9.1 Exclusive-OR Gates
		3.9.2 Multiplexer Circuit
	3.10 Implementation Details for SPLDs, CPLDs, and FPGAs
		3.10.1 Implementation in FPGAs
	3.11 Concluding Remarks
	3.12 Examples of Solved Problems
	Problems
	References
chapter 4: OPTIMIZED IMPLEMENTATION OF LOGIC FUNCTIONS
	4.1 Karnaugh Map
	4.2 Strategy for Minimization
		4.2.1 Terminology
		4.2.2 Minimization Procedure
	4.3 Minimization of Product-of-Sums Forms
	4.4 Incompletely Specified Functions
	4.5 Multiple-Output Circuits
	4.6 Multilevel Synthesis
		4.6.1 Factoring
		4.6.2 Functional Decomposition
		4.6.3 Multilevel NAND and NOR Circuits
	4.7 Analysis of Multilevel Circuits
	4.8 Cubical Representation
		4.8.1 Cubes and Hypercubes
	4.9 A Tabular Method for Minimization
		4.9.1 Generation of Prime Implicants
		4.9.2 Determination of a Minimum Cover
		4.9.3 Summary of the Tabular Method
	4.10 A Cubical Technique for Minimization
		4.10.1 Determination of Essential Prime Implicants
		4.10.2 Complete Procedure for Finding a Minimal Cover
	4.11 Practical Considerations
	4.12 Examples of Circuits Synthesized from VHDL Code
	4.13 Concluding Remarks
	4.14 Examples of Solved Problems
	Problems
	References
chapter 5: NUMBER REPRESENTATION AND ARITHMETIC CIRCUITS
	5.1 Number Representations in Digital Systems
		5.1.1 Unsigned Integers
		5.1.2 Octal and Hexadecimal Representations
	5.2 Addition of Unsigned Numbers
		5.2.1 Decomposed Full-Adder
		5.2.2 Ripple-Carry Adder
		5.2.3 Design Example
	5.3 Signed Numbers
		5.3.1 Negative Numbers
		5.3.2 Addition and Subtraction
		5.3.3 Adder and Subtractor Unit
		5.3.4 Radix-Complement Schemes
		5.3.5 Arithmetic Overflow
		5.3.6 Performance Issues
	5.4 Fast Adders
		5.4.1 Carry-Lookahead Adder
	5.5 Design of Arithmetic Circuits Using CAD Tools
		5.5.1 Design of Arithmetic Circuits Using Schematic Capture
		5.5.2 Design of Arithmetic Circuits Using VHDL
		5.5.3 Representation of Numbers in VHDL Code
		5.5.4 Arithmetic Assignment Statements
	5.6 Multiplication
		5.6.1 Array Multiplier for Unsigned Numbers
		5.6.2 Multiplication of Signed Numbers
	5.7 Other Number Representations
		5.7.1 Fixed-Point Numbers
		5.7.2 Floating-Point Numbers
		5.7.3 Binary-Coded-Decimal Representation
	5.8 ASCII Character Code
	5.9 Examples of Solved Problems
	Problems
	References
chapter 6: COMBINATIONAL-CIRCUIT BUILDING BLOCKS
	6.1 Multiplexers
		6.1.1 Synthesis of Logic Functions Using Multiplexers
		6.1.2 Multiplexer Synthesis Using Shannon’s Expansion
	6.2 Decoders
		6.2.1 Demultiplexers
	6.3 Encoders
		6.3.1 Binary Encoders
		6.3.2 Priority Encoders
	6.4 Code Converters
	6.5 Arithmetic Comparison Circuits
	6.6 VHDL for Combinational Circuits
		6.6.1 Assignment Statements
		6.6.2 Selected Signal Assignment
		6.6.3 Conditional Signal Assignment
		6.6.4 Generate Statements
		6.6.5 Concurrent and Sequential Assignment Statements
		6.6.6 Process Statement
		6.6.7 Case Statement
		6.6.8 VHDL Operators
	6.7 Concluding Remarks
	6.8 Examples of Solved Problems
	Problems
	References
chapter 7: FLIP-FLOPS, REGISTERS, COUNTERS, AND A SIMPLE PROCESSOR
	7.1 Basic Latch
	7.2 Gated SR Latch
		7.2.1 Gated SR Latch with NAND Gates
	7.3 Gated D Latch
		7.3.1 Effects of Propagation Delays
	7.4 Master-Slave and Edge-Triggered D Flip-Flops
		7.4.1 Master-Slave D Flip-Flop
		7.4.2 Edge-Triggered D Flip-Flop
		7.4.3 D Flip-Flops with Clear and Preset
		7.4.4 Flip-Flop Timing Parameters
	7.5 T Flip-Flop
		7.5.1 Configurable Flip-Flops
	7.6 JK Flip-Flop
	7.7 Summary of Terminology
	7.8 Registers
		7.8.1 Shift Register
		7.8.2 Parallel-Access Shift Register
	7.9 Counters
		7.9.1 Asynchronous Counters
		7.9.2 Synchronous Counters
		7.9.3 Counters with Parallel Load
	7.10 Reset Synchronization
	7.11 Other Types of Counters
		7.11.1 BCD Counter
		7.11.2 Ring Counter
		7.11.3 Johnson Counter
		7.11.4 Remarks on Counter Design
	7.12 Using Storage Elements with CAD Tools
		7.12.1 Including Storage Elements in Schematics
		7.12.2 Using VHDL Constructs for Storage Elements
	7.13 Using Registers and Counters with CAD Tools
		7.13.1 Including Registers and Counters in Schematics
		7.13.2 Registers and Counters in VHDL Code
		7.13.3 Using VHDL Sequential Statements for Registers and Counters
	7.14 Design Examples
		7.14.1 Bus Structure
		7.14.2 Simple Processor
		7.14.3 Reaction Timer
		7.14.4 Register Transfer Level (RTL) Code
	7.15 Timing Analysis of Flip-flop Circuits
	7.16 Concluding Remarks
	7.17 Examples of Solved Problems
	Problems
	References
chapter 8: SYNCHRONOUS SEQUENTIAL CIRCUITS
	8.1 Basic Design Steps
		8.1.1 State Diagram
		8.1.2 State Table
		8.1.3 State Assignment
		8.1.4 Choice of Flip-Flops and Derivation of Next-State and Output Expressions
		8.1.5 Timing Diagram
		8.1.6 Summary of Design Steps
	8.2 State-Assignment Problem
		8.2.1 One-Hot Encoding
	8.3 Mealy State Model
	8.4 Design of Finite State Machines Using CAD Tools
		8.4.1 VHDL Code for Moore-Type FSMs
		8.4.2 Synthesis of VHDL Code
		8.4.3 Simulating and Testing the Circuit
		8.4.4 An Alternative Style of VHDL Code
		8.4.5 Summary of Design Steps When Using CAD Tools
		8.4.6 Specifying the State Assignment in VHDL Code
		8.4.7 Specification of Mealy FSMs Using VHDL
	8.5 Serial Adder Example
		8.5.1 Mealy-Type FSM for Serial Adder
		8.5.2 Moore-Type FSM for Serial Adder
		8.5.3 VHDL Code for the Serial Adder
	8.6 State Minimization
		8.6.1 Partitioning Minimization Procedure
		8.6.2 Incompletely Specified FSMs
	8.7 Design of a Counter Using the Sequential Circuit Approach
		8.7.1 State Diagramand State Table for a Modulo-8 Counter
		8.7.2 State Assignment
		8.7.3 Implementation Using D-Type Flip-Flops
		8.7.4 Implementation Using JK-Type Flip-Flops
		8.7.5 Example—A Different Counter
	8.8 FSM as an Arbiter Circuit
		8.8.1 Implementation of the Arbiter Circuit
		8.8.2 Minimizing the Output Delays for an FSM
		8.8.3 Summary
	8.9 Analysis of Synchronous Sequential Circuits
	8.10 Algorithmic State Machine (ASM) Charts
	8.11 Formal Model for Sequential Circuits
	8.12 Concluding Remarks
	8.13 Examples of Solved Problems
	Problems
	References
chapter 9: ASYNCHRONOUS SEQUENTIAL CIRCUITS
	9.1 Asynchronous Behavior
	9.2 Analysis of Asynchronous Circuits
	9.3 Synthesis of Asynchronous Circuits
	9.4 State Reduction
	9.5 State Assignment
		9.5.1 Transition Diagram
		9.5.2 Exploiting Unspecified Next-State Entries
		9.5.3 State Assignment Using Additional State Variables
		9.5.4 One-Hot State Assignment
	9.6 Hazards
		9.6.1 Static Hazards
		9.6.2 Dynamic Hazards
		9.6.3 Significance of Hazards
	9.7 A Complete Design Example
		9.7.1 The Vending-Machine Controller
	9.8 Concluding Remarks
	9.9 Examples of Solved Problems
	Problems
	References
chapter 10: DIGITAL SYSTEM DESIGN
	10.1 Building Block Circuits
		10.1.1 Flip-Flops and Registers with Enable Inputs
		10.1.2 Shift Registers with Enable Inputs
		10.1.3 Static Random Access Memory (SRAM)
		10.1.4 SRAM Blocks in PLDs
	10.2 Design Examples
		10.2.1 A Bit-Counting Circuit
		10.2.2 ASM Chart Implied Timing Information
		10.2.3 Shift-and-Add Multiplier
		10.2.4 Divider
		10.2.5 Arithmetic Mean
		10.2.6 Sort Operation
	10.3 Clock Synchronization
		10.3.1 Clock Skew
		10.3.2 Flip-Flop Timing Parameters
		10.3.3 Asynchronous Inputs to Flip-Flops
		10.3.4 Switch Debouncing
	10.4 Concluding Remarks
	Problems
	References
chapter 11: TESTING OF LOGIC CIRCUITS
	11.1 Fault Model
		11.1.1 Stuck-at Model
		11.1.2 Single and Multiple Faults
		11.1.3 CMOS Circuits
	11.2 Complexity of a Test Set
	11.3 Path Sensitizing
		11.3.1 Detection of a Specific Fault
	11.4 Circuits with Tree Structure
	11.5 Random Tests
	11.6 Testing of Sequential Circuits
		11.6.1 Design for Testability
	11.7 Built-in Self-Test
		11.7.1 Built-in Logic Block Observer
		11.7.2 Signature Analysis
		11.7.3 Boundary Scan
	11.8 Printed Circuit Boards
		11.8.1 Testing of PCBs
		11.8.2 Instrumentation
	11.9 Concluding Remarks
	Problems
	References
chapter 12: COMPUTER AIDED DESIGN TOOLS
	12.1 Synthesis
		12.1.1 Netlist Generation
		12.1.2 Gate Optimization
		12.1.3 Technology Mapping
	12.2 Physical Design
		12.2.1 Placement
		12.2.2 Routing
		12.2.3 Static Timing Analysis
	12.3 Concluding Remarks
	References
appendix A VHDL REFERENCE
	A.1 Documentation in VHDL Code
	A.2 Data Objects
		A.2.1 Data Object Names
		A.2.2 Data Object Values and Numbers
		A.2.3 SIGNAL Data Objects
		A.2.4 BIT and BIT_VECTOR Types
		A.2.5 STD_LOGIC and STD_LOGIC_VECTOR Types
		A.2.6 STD_ULOGIC Type
		A.2.7 SIGNED and UNSIGNED Types
		A.2.8 INTEGER Type
		A.2.9 BOOLEAN Type
		A.2.10 ENUMERATION Type
		A.2.11 CONSTANT Data Objects
		A.2.12 VARIABLE Data Objects
		A.2.13 Type Conversion
		A.2.14 Arrays
	A.3 Operators
	A.4 VHDL Design Entity
		A.4.1 ENTITY Declaration
		A.4.2 Architecture
	A.5 Package
	A.6 Using Subcircuits
		A.6.1 Declaring a COMPONENT in a Package
	A.7 Concurrent Assignment Statements
		A.7.1 Simple Signal Assignment
		A.7.2 Assigning Signal Values Using OTHERS
		A.7.3 Selected Signal Assignment
		A.7.4 Conditional Signal Assignment
		A.7.5 GENERATE Statement
	A.8 Defining an Entity with GENERICs
	A.9 Sequential Assignment Statements
		A.9.1 PROCESS Statement
		A.9.2 IF Statement
		A.9.3 CASE Statement
		A.9.4 Loop Statements
		A.9.5 Using a Process for a Combinational Circuit
		A.9.6 Statement Ordering
		A.9.7 Using a VARIABLE in a PROCESS
	A.10 Sequential Circuits
		A.10.1 A Gated D Latch
		A.10.2 D Flip-Flop
		A.10.3 Using a WAIT UNTIL Statement
		A.10.4 A Flip-Flop with Asynchronous Reset
		A.10.5 Synchronous Reset
		A.10.6 Registers
		A.10.7 Shift Registers
		A.10.8 Counters
		A.10.9 Using Subcircuits with GENERIC Parameters
		A.10.10 A Moore-Type Finite State Machine
		A.10.11 A Mealy-Type Finite State Machine
	A.11 Common Errors in VHDL Code
	A.12 Concluding Remarks
	References
appendix B TUTORIAL 1—INTRODUCTION TO QUARTUS II CAD SOFTWARE
	B.1 Introduction
		B.1.1 Getting Started
	B.2 Starting a New Project
	B.3 Design Entry Using Schematic Capture
		B.3.1 Using the Block Editor
		B.3.2 Synthesizing a Circuit from the Schematic
		B.3.3 Simulating the Designed Circuit
	B.4 Design Entry Using VHDL
		B.4.1 Create Another Project
		B.4.2 Using the Text Editor
		B.4.3 Synthesizing a Circuit from the VHDL Code
		B.4.4 Performing Functional Simulation
		B.4.5 Using Quartus II to Debug VHDL Code
	B.5 Mixing Design-Entry Methods
		B.5.1 Using Schematic Entry at the Top Level
		B.5.2 Using VHDL at the Top Level
	B.6 Quartus II Windows
	B.7 Concluding Remarks
appendix C TUTORIAL 2—IMPLEMENTING CIRCUITS IN ALTERA DEVICES
	C.1 Implementing a Circuit in a Cyclone II FPGA
		C.1.1 Selecting a Chip
		C.1.2 Compiling the Project
		C.1.3 Performing Timing Simulation
		C.1.4 Using the Chip Planner
	C.2 Making Pin Assignments
		C.2.1 Recompiling the Project with Pin Assignments
	C.3 Programming and Configuring the FPGA Device
		C.3.1 JTAG Programming
	C.4 Concluding Remarks
appendix D TUTORIAL 3—USING  QUARTUS II TOOLS
	D.1 Implementing an Adder using Quartus II
		D.1.1 Simulating the Circuit
		D.1.2 Timing Simulation
		D.1.3 Implementing the Adder Circuit on the DE2 Board
	D.2 Using an LPM Module
	D.3 Design of a Finite State Machine
	D.4 Concluding Remarks
appendix E COMMERCIAL DEVICES
	E.1 Simple PLDs
		E.1.1 The 22V10 PAL Device
	E.2 Complex PLDs
		E.2.1 Altera MAX 7000
	E.3 Field-Programmable Gate Arrays
		E.3.1 Altera FLEX 10K
		E.3.2 Xilinx XC4000
		E.3.3 Altera APEX 20K
		E.3.4 Altera Stratix
		E.3.5 Altera Cyclone, Cyclone II, and Cyclone III
		E.3.6 Altera Stratix II and Stratix III
		E.3.7 Xilinx Virtex
		E.3.8 Xilinx Virtex-II, Virtex-II Pro, Virtex-4, and Virtex-5
		E.3.9 Xilinx Spartan-3
	E.4 Transistor-Transistor Logic
		E.4.1 TTL Circuit Families
	References
ANSWERS
INDEX