مشخصات کتاب

Fundamentals of Computer Architecture and Design

ویرایش: 2nd 
نویسندگان: Ahmet Bindal  
سری:  
ISBN (شابک) : 9783030002220 
ناشر: Springer 
سال نشر: 2019 
تعداد صفحات: 603 
زبان: English 
فرمت فایل : PDF (درصورت درخواست کاربر به PDF، EPUB یا AZW3 تبدیل می شود) 
حجم فایل: 27 مگابایت 

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توضیحاتی درمورد کتاب به خارجی

This book is written for young professionals and graduate students who have prior logic design background and want to learn how to use logic blocks to build a complete system from design specifications. My two-decade-long industry experience has taught me that engineers are “shape-oriented” people, and that they tend to learn from charts and diagrams. Therefore, the teaching method you will see in this textbook caters this mid-set: a lot of circuit schematics, block diagrams, timing diagrams, and examples supported by minimal text. The book has eight chapters. The first three chapters give a complete review of the logic design principles since rest of the chapters significantly depend on this review. Chapter 1 concentrates on the combinational logic design. It describes basic logic gates, De Morgan’s theorem, truth tables, and logic minimization. The chapter uses these key concepts in order to design megacells, namely various types of adders and multipliers. Chapter 2 introduces sequential logic components, namely latches, flip-flops, registers and counters. It introduces the concept of timing diagrams to explain the functionality of each logic block. Moore and Mealy-type state machines, counter– decoder-type controllers, and the construction of simple memories are also explained in this chapter. Chapter 2 is the first chapter that illustrates the design process: how to develop architectural logic blocks using timing diagrams and how to build a controller from a timing diagram to govern data flow. Chapter 3 focuses on the review of asynchronous logic design, which includes state definitions, primitive flow tables, and state minimization. Racing conditions in asynchronous designs, how to detect and correct them are also explained in this chapter. The chapter ends with designing an important asynchronous timing block: the C (or the Mueller) element and describes an asynchronous timing methodology that leads to a complete design using timing diagrams. From Chaps. 4 to 8, computer architecture-related topics are covered. Chapter 4 examines a very essential system element: system bus and communication protocols between system modules. This chapter studies parallel and serial bus architectures, defines bus master and bus slave concepts, and examines their bus interfaces. Read and write bus protocols, bus handover, and bus arbitration are also examined in this chapter. System memories, namely static random-access memory (SRAM), synchronous dynamicrandom access memory (SDRAM), electrically erasable programmable read-only memory (E2PROM), and flash memory are examined in Chap. 5. This chapter also shows how to design bus interface for each memory type using timing diagrams and state machines. Chapter 6 is about the design of a simple reduced instruction set computer (RISC) central processing unit (CPU). This chapter has been expanded in the second edition to cover a variety of subjects in the floating-point unit and cache memory. In the first part of this chapter, fixed-point instructions are introduced. This section first develops a dedicated hardware (data-path) to execute each RISC instruction and then groups several instructions together in a set and designs a common data-path to execute user programs that use this instruction set. In this section, fixed-point-related structural, data and program control hazards are described, and the methods of how to prevent each type are explained. The second part of this chapter is dedicated to the IEEE single and double-precision floating-point formats, leading to the simplified designs of floating-point adder and multiplier. These designs are then integrated with the fixed-point hardware to obtain a RISC CPU capable of executing both fixed-point and floating-point arithmetic instructions. In the same section, floating-point-related data hazards are described. A new floating-point architecture is proposed based on a simplified version of the Tomasulo algorithm in order to reduce and eliminate these hazards. In the third part, various techniques to increase the program execution efficiency are discussed. The trade-offs between static and dynamic pipelines, single-issue versus dual-issue and triple-issue pipelines are explained with examples. Compiler enhancement techniques, such as loop unrolling and dynamic branch prediction methods, are illustrated to reduce overall CPU execution time. The last section of this chapter explains different types of cache memory architectures, including direct-mapped, set-associative and fully associative caches, their operation and the trade-off between each cache structure. The write-through and write-back mechanisms are discussed and compared with each other, using design examples. Furthermore, Chap. 6 now contains static and dynamic, single and multiple issue CPUs, the advantages of out-of-order execution and register renaming. The final phase of this chapter is dedicated to multi-core CPUs with a central memory and distributed memories. The data update and replacement policy are described for each CPU architecture to maintain cache coherency. The design of system peripherals, namely direct memory access (DMA), interrupt controller, system timers, serial interface, display adapter, and data controllers are covered in Chap. 7. The interrupt controller has been expanded in this new edition to cover context switching. The design methodology for constructing the data-paths using timing diagrams shown in Chap. 2 is closely followed to design the bus interface for each peripheral in this chapter. Chapter 8 describes the field-programmable gate array (FPGA), and the fundamentals of data-driven processors as special topics. At the end of the book, there is a small appendix that introduces the Verilog language. Verilog is a widely used Hardware Design Language (HDL) to build and verify logic blocks, mega cells and systems. Interested readers are encouraged to go one step beyond and learn system Verilog to be able to verify large logic blocks.

فهرست مطالب

Front Matter ....Pages i-xiv
 Review of Combinational Logic Circuits  (Ahmet Bindal)....Pages 1-60
 Review of Sequential Logic Circuits  (Ahmet Bindal)....Pages 61-100
 Review of Asynchronous Logic Circuits  (Ahmet Bindal)....Pages 101-118
 System Bus  (Ahmet Bindal)....Pages 119-150
 Memory Circuits and Systems  (Ahmet Bindal)....Pages 151-250
 Central Processing Unit  (Ahmet Bindal)....Pages 251-438
 System Peripherals  (Ahmet Bindal)....Pages 439-516
 Special Topics  (Ahmet Bindal)....Pages 517-549
Back Matter ....Pages 551-592

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