FPGA Express VHDL Reference Manual

Software Manuals Online......Page 0
VHDL Reference Manual......Page 1
About This Manual......Page 3
Declarations 2-10......Page 9
Array Attributes 3-12......Page 10
Unary (Signed) Operators 4-10......Page 11
Indexed Name Targets 5-4......Page 12
Function Calls 5-41......Page 13
Direct Instantiation 6-25......Page 14
Inferring a Simple Three-State Driver 7-60......Page 15
Asynchronous Behavior 8-37......Page 16
Implementation A-39......Page 17
Using the Package B-21......Page 18
Operands and Expressions C-12......Page 19
VHDL Reserved Words C-17......Page 20
Figure 52 Schematic Design From Example 58 5-16......Page 21
Figure 610 Design of COMP Components Connecting Bit Vectors A and B 6-30......Page 22
Figure 722 Toggle Flip-Flop With Enable and Asynchronous Reset 7-51......Page 23
Figure 814 Schematic of Synchronous Counter With Reset and Enable 8- 24......Page 24
Figure A18 Serial-to-Parallel Converter—Shifting Bits Schematic A-50......Page 25
Figure A19 Programmable Logic Array Schematic A-55......Page 26
Table C1 VHDL Reserved Words C-17......Page 27
Example 216 Operator Overloading 2-30......Page 29
Example 317 FPGA Compiler II / FPGA Express STANDARD Package 3- 17......Page 30
Example 421 A Qualified Decimal Literal 4-30......Page 31
Example 518 Procedure Call to Sort an Array 5-40......Page 32
Example 611 Conditional Signal Assignment 6-19......Page 33
Example 713 D Latch With Asynchronous Set and Reset 7-18......Page 34
Example 731 Inference Report for a D Flip-Flop With Asynchronous Reset 7-31......Page 35
Example 749 Inference Report for a Toggle Flip-Flop With Asynchronous Reset 7-48......Page 36
Example 767 Inference Report for Three-State Driver Without Registered Enable 7-68......Page 37
Example 821 Using don’t care Type for Seven-Segment LED Decoder 8- 29......Page 38
Example B5 Binary Arithmetic Functions B-11......Page 39
Example B28 Boolean Reduction Operations B-31......Page 40
Example C3 Sample Showing Use of xnor Operator C-11......Page 41
Using FPGA Compiler II / FPGA Express with VHDL......Page 43
Hardware Description Languages......Page 44
Advantages of HDLs......Page 45
About VHDL......Page 46
FPGA Compiler II / FPGA Express Design Process......Page 49
Using FPGA Compiler II / FPGA Express to Compile a VHDL Design......Page 50
Design Methodology......Page 51
Design Descriptions......Page 53
Entities......Page 54
Entity Generic Specifications......Page 55
Entity Port Specifications......Page 56
Architecture......Page 57
Declarations......Page 62
Examples of Architectures for NAND2 Entity......Page 85
Configurations......Page 86
Package Uses......Page 87
Package Structure......Page 88
Package Declarations......Page 89
Package Body......Page 91
Resolution Functions......Page 92
Data Types......Page 97
Enumeration Types......Page 99
Enumeration Encoding......Page 100
Enumeration Encoding Values......Page 103
Integer Types......Page 104
Array Types......Page 105
Unconstrained Arrays......Page 106
Array Attributes......Page 108
Record Types......Page 109
Record Aggregates......Page 110
Predefined VHDL Data Types......Page 112
Data Type CHARACTER......Page 114
Data Type BIT_VECTOR......Page 115
File Types......Page 116
Subtypes......Page 117
Expressions......Page 121
Operators......Page 122
Logical Operators......Page 123
Relational Operators......Page 125
Adding Operators......Page 128
Unary (Signed) Operators......Page 130
Multiplying Operators......Page 131
Miscellaneous Arithmetic Operators......Page 132
Operands......Page 134
Operand Bit-Width......Page 135
Computable Operands......Page 136
Aggregates......Page 138
Attributes......Page 140
Expressions......Page 141
Function Calls......Page 142
Identifiers......Page 143
Indexed Names......Page 144
Literals......Page 146
Qualified Expressions......Page 149
Records and Fields......Page 150
Slice Names......Page 152
Type Conversions......Page 154
Sequential Statements......Page 157
Assignment Statements and Targets......Page 158
Simple Name Targets......Page 159
Indexed Name Targets......Page 160
Slice Targets......Page 163
Field Targets......Page 164
Aggregate Targets......Page 165
Variable Assignment Statements......Page 167
Signal Assignment Statements......Page 168
Evaluating Conditions......Page 171
Using the if Statement to Infer Registers and Latches......Page 172
case Statements......Page 173
Using Different Expression Types......Page 174
Invalid case Statements......Page 177
loop Statements......Page 178
Basic loop Statements......Page 179
while...loop Statements......Page 180
for...loop Statements......Page 181
next Statements......Page 186
exit Statements......Page 189
Subprogram Declaration and Body......Page 191
Subprogram Calls......Page 193
return Statement......Page 199
Procedures and Functions as Design Components......Page 201
Example With Component Implication Directives......Page 203
Example Without Component Implication Directives......Page 205
wait Statements......Page 206
Inferring Synchronous Logic......Page 207
Combinational Versus Sequential Processes......Page 211
null Statements......Page 214
Concurrent Statements......Page 217
process Statements......Page 218
Combinational Process Example......Page 221
Sequential Process Example......Page 222
Driving Signals......Page 224
block Statements......Page 226
Nested Blocks......Page 227
Guarded Blocks......Page 228
Concurrent Versions of Sequential Statements......Page 229
Concurrent Procedure Calls......Page 230
Concurrent Signal Assignments......Page 233
Component Instantiation Statements......Page 238
Direct Instantiation......Page 241
for...generate Statement......Page 242
if...generate Statements......Page 247
Register Inference......Page 251
The inference Report......Page 253
Controlling Register Inference......Page 254
Inferring Latches......Page 258
Inferring Flip-Flops......Page 271
Understanding Limitations of Register Inference......Page 307
Reporting Three-State Inference......Page 309
Inferring Three-State Drivers......Page 310
Understanding the Limitations of Three-State Inference......Page 319
Writing Circuit Descriptions......Page 321
How Statements Are Mapped to Logic......Page 322
Adding Structure......Page 323
Optimizing Arithmetic Expressions......Page 326
Changing an Operator Bit-Width......Page 334
Using State Information......Page 337
Propagating Constants......Page 341
Sharing Complex Operators......Page 342
Asynchronous Designs......Page 343
Don’t Care Inference......Page 349
Using don’t care Default Values......Page 352
Differences Between Simulation and Synthesis......Page 353
Feedback Paths and Latches......Page 354
Understanding Superset Issues and Error Checking......Page 358
FPGA Compiler II / FPGA Express Directives......Page 359
FPGA Compiler II / FPGA Express Directives......Page 360
synthesis_off and synthesis_on Directives......Page 361
Component Implication Directives......Page 363
Examples......Page 365
Moore Machine......Page 366
Mealy Machine......Page 369
Read-Only Memory......Page 371
Waveform Generator......Page 374
Smart Waveform Generator......Page 377
Definable-Width Adder-Subtracter......Page 380
Count Zeros—Combinational Version......Page 383
Count Zeros—Sequential Version......Page 386
Soft Drink Machine—State Machine Version......Page 388
Soft Drink Machine—Count Nickels Version......Page 393
Carry Value Computations......Page 396
Implementation......Page 403
Serial-to-Parallel Converter—Counting Bits......Page 404
Input Format......Page 405
Implementation Details......Page 406
Serial-to-Parallel Converter—Shifting Bits......Page 411
Programmable Logic Arrays......Page 415
Synopsys Packages......Page 421
std_logic_1164 Package......Page 422
std_logic_arith Package......Page 423
Using the Package......Page 424
Modifying the Package......Page 425
Data Types......Page 426
Conversion Functions......Page 428
Arithmetic Functions......Page 430
Comparison Functions......Page 433
Shift Functions......Page 435
pragma built_in......Page 437
numeric_std Package......Page 440
Data Types......Page 441
Resize Function......Page 442
Arithmetic Functions......Page 443
Comparison Functions......Page 444
Shift Functions......Page 446
Rotate Functions......Page 447
Shift and Rotate Operators......Page 448
std_logic_misc Package......Page 450
ATTRIBUTES Package......Page 451
VHDL Constructs......Page 453
VHDL Construct Support......Page 454
Design Units......Page 455
Data Types......Page 456
Declarations......Page 457
Specifications......Page 458
Names......Page 459
Identifiers and Extended Identifiers......Page 460
Operators......Page 461
Operands and Expressions......Page 464
Sequential Statements......Page 465
Concurrent Statements......Page 467
Predefined Language Environment......Page 468
VHDL Reserved Words......Page 469