Field-Programmable Logic Smart Applications, New Paradigms and Compilers: 6th International Workshop on Field-Programmable Logic and Applications, FPL '96 Darmstadt, Germany, September 23–25, 1996 Proceedings

Portable pipeline synthesis for FCCMs....Pages 1-13
Performance-directed technology mapping for LUT-based FPGAs — What role do decomposition and covering play?....Pages 14-23
A framework for developing parametrised FPGA libraries....Pages 24-33
FACT: Co-evaluation environment for FPGA architecture and CAD system....Pages 34-43
An universal CLA adder generator for SRAM-based FPGAs....Pages 44-54
An emulation system of the WASMII: A data driven computer on a virtual hardware....Pages 55-64
Costum computing machines vs. Hardware/Software Co-Design: From a globalized point of view....Pages 65-76
The design of a coprocessor board using Xilinx\'s XC6200 FPGA — An experience report....Pages 77-86
RACE: Reconfigurable and adaptive computing environment....Pages 87-95
Computing 2-D DFTs using FPGAs....Pages 96-105
CAPpartx: Computer aided prototyping partitioning for Xilinx FPGAs, a hierarchical partitioning tool for rapid prototyping....Pages 106-115
Architectural synthesis and efficient circuit implementation for field programmable gate arrays....Pages 116-125
RaPiD — Reconfigurable pipelined datapath....Pages 126-135
Solving satisfiability problems on FPGAs....Pages 136-145
FPGA implementation of the block-matching algorithm for motion estimation in image coding....Pages 146-155
Parallel CRC computation in FPGAs....Pages 156-165
Coherent demodulation with FPGAs....Pages 166-175
The Trianus system and its application to custom computing....Pages 176-184
Logic synthesis for FPGAs using a mixed exclusive-/inclusive-OR form....Pages 185-192
Flexible codesign target architecture for early prototyping of CMIST systems....Pages 193-199
Attempt-1: A reconfigurable multiprocessor testbed....Pages 200-209
A slow motion engine for the analysis of FPGA-based prototypes....Pages 210-219
Implementing reconfigurable datapaths in FPGAs for adaptive filter design....Pages 220-229
A fast constant coefficient multiplier for the XC6200....Pages 230-236
Key issues for user acceptance of FPGA design tools....Pages 237-241
Reconfigurable DSP demonstrators for the development of spacecraft payload processors....Pages 242-251
Reconfigurable logic based fibre channel network card with sub 2 μs raw latency....Pages 252-259
An asynchronous transfer mode (ATM) stream demultiplexer and switch....Pages 260-269
Optically reconfigurable FPGAs: Is this a future trend?....Pages 270-279
CCSimP — An instruction-level costum-configurable processor for FPLDs....Pages 280-289
Architectural synthesis techniques for dynamically reconfigurable logic....Pages 290-296
Fast reconfigurable crossbar switching in FPGAs....Pages 297-306
Growable FPGA macro generator....Pages 307-316
Architectural strategies for implementing an image processing algorithm on XC6000 FPGA....Pages 317-326
A virtual hardware operating system for the Xilinx XC6200....Pages 327-336
An experimental programmable environment for prototyping digital circuits....Pages 337-345
Migration from schematic-based designs to a VHDL synthesis environment....Pages 346-355
ASIC design and FPGA design: A unified design methodology applied to different technologies....Pages 356-360
FIR filtering with FPGAs using quadrature sigma-delta modulation encoding....Pages 361-365
A new FPGA technology mapping approach by cluster merging....Pages 366-370
An EPLD based transient recorder for simulation of video signal processing devices in a VHDL environment close to system level conditions....Pages 371-375
Convolutional error decoding with FPGAs....Pages 376-380
Metastability characteristics testing for programmable logic design....Pages 381-388
Implementing ΣΔ modulator prototype designs on an FPGA....Pages 389-393
Design of a VME parameterized library for FPGAs....Pages 394-399
Development of a telephone answering machine in a lab — FPGAs in Education....Pages 400-404
FPGA design migration: Some remarks....Pages 405-409
Concurrent design of hardware/software dedicated systems....Pages 410-414
The implementation of a field programmable logic based co-processor for the acceleration of discrete event simulators....Pages 415-424
Computing weight distributions of binary linear block codes on a CCM....Pages 425-430