Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing: 10th International Conference, FPL 2000 Villach, Austria, August 27–30, 2000 Proceedings

The Rising Wave of Field Programmability....Pages 1-6
Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS....Pages 7-18
A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization....Pages 19-28
A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors....Pages 29-38
Reconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits....Pages 39-47
Internet Connected FPL....Pages 48-57
Field Programmable Communication Emulation and Optimization for Embedded System Design....Pages 58-67
FPGA-Based Emulation: Industrial and Custom Prototyping Solutions....Pages 68-77
FPGA-Based Prototyping for Product Definition....Pages 78-86
Implementation of Virtual Circuits by Means of the FIPSOC Devices....Pages 87-95
Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT....Pages 96-105
A Self-Reconfigurable Gate Array Architecture....Pages 106-120
Multitasking on FPGA Coprocessors....Pages 121-130
Design Visualisation for Dynamically Reconfigurable Systems....Pages 131-140
Verification of Dynamically Reconfigurable Logic....Pages 141-150
Design of a Fault Tolerant FPGA....Pages 151-156
Real-Time Face Detection on a Configurable Hardware System....Pages 157-162
Multifunctional Programmable Single-Board CAN Monitoring Module....Pages 163-168
Self-Testing of Linear Segments in User-Programmed FPGAs....Pages 169-174
Implementing a Fieldbus Interface Using an FPGA....Pages 175-180
Area-Optimized Technology Mapping for Hybrid FPGAs....Pages 181-190
CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs....Pages 191-200
Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards....Pages 201-210
A Placement Algorithm for FPGA Designs with Multiple I/O Standards....Pages 211-220
A Mapping Methodology for Code Trees onto LUT-Based FPGAs....Pages 221-229
Possibilities and Limitations of Applying Evolvable Hardware to Real-World Applications....Pages 230-239
A Co-processor System with a Virtex FPGA for Evolutionary Computation....Pages 240-249
System Design with Genetic Algorithms....Pages 250-259
Implementing Kak Neural Networks on a Reconfigurable Computing Platform....Pages 260-269
Compact Spiking Neural Network Implementation in FPGA....Pages 270-276
Silicon Platforms for the Next Generation Wireless Systems — What Role Does Reconfigurable Hardware Play?....Pages 277-285
From Reconfigurability to Evolution in Construction Systems: Spanning the Electronic, Microfluidic and Biomolecular Domains....Pages 286-299
A Specific Test Methodology for Symmetric SRAM-Based FPGAs....Pages 300-311
DReAM : A Dynamica lly Reconfigura bl e Architecture for Fut ur e Mobile Communication Applications....Pages 312-321
Fast Carrier and Phase Synchronization Units for Digital Receivers Based on Re-configurable Logic....Pages 322-331
Software Radio Reconfigurable Hardware System (SHaRe)....Pages 332-341
Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform....Pages 342-351
Partial Run-Time Reconfiguration Using JRTR....Pages 352-360
A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems....Pages 361-370
A Hybrid Prototyping Platform for Dynamically Reconfigurable Designs....Pages 371-378
Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer....Pages 379-388
Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures....Pages 389-399
Mapping of DSP Algorithms on Field Programmable Function Arrays....Pages 400-411
On Availability of Bit-Narrow Operations in General-Purpose Applications....Pages 412-421
A Comparison of FPGA Implementations of Bit-Level and Word-Level Matrix Multipliers....Pages 422-431
A New Floorplanning Method for FPGA Architectural Research....Pages 432-442
Efficient Self-Reconfigurable Implementations Using On-chip Memory....Pages 443-448
Design and Implementation of an XC6216 FPGA Model in Verilog....Pages 449-455
Reusable DSP Functions in FPGAs....Pages 456-461
A Parallel Pipelined SAT Solver for FPGA’s....Pages 462-468
A Multi-node Dynamic Reconfigurable Computing System with Distributed Reconfiguration Controller....Pages 469-474
A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems....Pages 475-484
A CORDIC Arctangent FPGA Implementation for a High-Speed 3D-Camera System....Pages 485-494
Reconfigurable Computing for Speech Recognition: Preliminary Findings....Pages 495-504
Security Upgrade of Existing ISDN Devices by Using Reconfigurable Logic....Pages 505-514
The Fastest Multiplier on FPGAs with Redundant Binary Representation....Pages 515-524
High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs....Pages 525-534
Balancing Logic Utilization and Area Efficiency in FPGAs....Pages 535-544
Performance Penalty for Fault Tolerance in Roving STARs....Pages 545-554
Optimum Functional Decomposition for LUT-Based FPGA Synthesis....Pages 555-564
Optimization of Run-Time Reconfigurable Embedded Systems....Pages 565-574
It’s FPL, Jim — But Not as We Know It! Opportunities for the New Commercial Architectures....Pages 575-584
Reconfigurable Systems: New Activities in Asia....Pages 585-594
StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox....Pages 595-604
Stream Computations Organized for Reconfigurable Execution (SCORE)....Pages 605-614
Memory Access Schemes for Configurable Processors....Pages 615-625
Generating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory....Pages 626-635
Combining Serialisation and Reconfiguration for FPGA Designs....Pages 636-645
Multiple-Wordlength Resource Binding....Pages 646-655
Automatic Temporal Floorplanning with Guaranteed Solution Feasibility....Pages 656-664
A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology....Pages 665-674
Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPGAs....Pages 675-684
Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware....Pages 685-694
Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis....Pages 695-706
Behavioural Language Compilation with Virtual Hardware Management....Pages 707-717
Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs....Pages 718-727
Evaluation of Accelerator Designs for Subgraph Isomorphism Problem....Pages 729-738
The Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware....Pages 739-748
Multiplexer Based Reconfiguration for Virtex Multipliers....Pages 749-758
Efficient Building of Word Recognizer in FPGAs for Term-Document Matrices Construction....Pages 759-768
Reconfigurable Computing between Classifications and Metrics — The Approach of Space/Time-Scheduling....Pages 769-772
FPGA Implementation of a Prototype WDM On-Line Scheduler....Pages 773-776
An FPGA Based Scheduling Coprocessor for Dynamic Priority Scheduling in Hard Real-Time Systems....Pages 777-780
Formal Verification of a Reconfigurable Microprocessor....Pages 781-784
The Role of the Embedded Memories in the Implementation of Artificial Neural Networks....Pages 785-788
Programmable System Level Integration Brings System-on-Chip Design to the Desktop....Pages 789-792
On Applying Software Development Best Practice to FPGAs in Safety-Critical Systems....Pages 793-796
Pre-route Assistant: A Routing Tool for Run-Time Reconfiguration....Pages 797-800
High Speed Computation of Lattice Gas Automata with FPGA....Pages 801-804
An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture....Pages 805-809
FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers....Pages 810-813
Toward Uniform Approach to Design of Evolvable Hardware Based Systems....Pages 814-817
Educational Programmable Hardware Prototyping and Verification System....Pages 818-821
A Stream Processor Architecture Based on the Con.gurable CEPRA-S....Pages 822-825
An Innovative Approach to Couple EDA Tools with Recon.gurable Hardware....Pages 826-829
FPL Curriculum at Tallinn Technical University....Pages 830-833
The Modular Architecture of SYNTHUP, FPGA Based PCI Board for Real-Time Sound Synthesis and Digital Signal Processing....Pages 834-837
A Rapid Prototyping Environment for Microprocessor Based System-on-Chips and Its Application to the Development of a Network Processor....Pages 838-841
Configuration Prefetching for Non-deterministic Event Driven Multi-context Schedulers....Pages 842-845
Wireless Base Station Design Using a Reconfigurable Communications Processor....Pages 846-848
Placement of Linear Arrays....Pages 849-852