Field Programmable Logic and Application: 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003 Proceedings

Front Matter....Pages -
Reconfigurable Circuits Using Hybrid Hall Effect Devices....Pages 1-10
Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory....Pages 11-20
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture....Pages 21-30
Symbol Timing Synchronization in FPGA-Based Software Radios: Application to DVB-S....Pages 31-40
An Algorithm Designer’s Workbench for Platform FPGAs....Pages 41-50
Prototyping for the Concurrent Development of an IEEE 802.11 Wireless LAN Chipset....Pages 51-60
ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix....Pages 61-70
Inter-processor Connection Reconfiguration Based on Dynamic Look-Ahead Control of Multiple Crossbar Switches....Pages 71-80
Arbitrating Instructions in an ρμ -Coded CCM....Pages 81-90
How Secure Are FPGAs in Cryptographic Applications?....Pages 91-100
FPGA Implementations of the RC6 Block Cipher....Pages 101-110
Very High Speed 17 Gbps SHACAL Encryption Architecture....Pages 111-120
Track Placement: Orchestrating Routing Structures to Maximize Routability....Pages 121-130
Quark Routing....Pages 131-140
Global Routing for Lookup-Table Based FPGAs Using Genetic Algorithms....Pages 141-150
Virtualizing Hardware with Multi-context Reconfigurable Arrays....Pages 151-160
A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device....Pages 161-170
Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device....Pages 171-180
Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES....Pages 181-193
Using Partial Reconfiguration in Cryptographic Applications: An Implementation of the IDEA Algorithm....Pages 194-203
An Implementation Comparison of an IDEA Encryption Cryptosystem on Two General-Purpose Reconfigurable Computers....Pages 204-219
Data Processing System with Self-reconfigurable Architecture, for Low Cost, Low Power Applications....Pages 220-229
Low Power Coarse-Grained Reconfigurable Instruction Set Processor....Pages 230-239
Encoded-Low Swing Technique for Ultra Low Power Interconnect....Pages 240-251
Building Run-Time Reconfigurable Systems from Tiles....Pages 252-261
Exploiting Redundancy to Speedup Reconfiguration of an FPGA....Pages 262-271
Run-Time Exchange of Mechatronic Controllers Using Partial Hardware Reconfiguration....Pages 272-281
Efficient Modular-Pipelined AES Implementation in Counter Mode on ALTERA FPGA....Pages 282-291
An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm....Pages 292-302
Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core....Pages 303-312
Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations....Pages 313-323
Branch Optimisation Techniques for Hardware Compilation....Pages 324-333
A Model for Hardware Realization of Kernel Loops....Pages 334-344
Programmable Asynchronous Pipeline Arrays....Pages 345-354
Globally Asynchronous Locally Synchronous FPGA Architectures....Pages 355-364
Case Study of a Functional Genomics Application for an FPGA-Based Coprocessor....Pages 365-374
A Smith-Waterman Systolic Cell....Pages 375-384
Software Decelerators....Pages 385-395
A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer....Pages 396-405
Extra-dimensional Island-Style FPGAs....Pages 406-415
Using Multiplexers for Control and Data in D-Fabrix....Pages 416-425
Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics....Pages 426-436
A Real-Time Visualization System for PIV....Pages 437-447
A Real-Time Stereo Vision System with FPGA....Pages 448-457
Synthesizing on a Reconfigurable Chip an Autonomous Robot Image Processing System....Pages 458-467
Reconfigurable Hardware SAT Solvers: A Survey of Systems....Pages 468-477
Fault Tolerance Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques....Pages 478-487
Hardware Implementations of Real-Time Reconfigurable WSAT Variants....Pages 488-496
Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements....Pages 497-506
Time and Energy Efficient Matrix Factorization Using FPGAs....Pages 507-519
Improving DSP Performance with a Small Amount of Field Programmable Logic....Pages 520-532
Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA....Pages 533-542
An FPGA System for the High Speed Extraction, Normalization and Classification of Moment Descriptors....Pages 543-552
Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs....Pages 553-564
A Self-reconfiguring Platform....Pages 565-574
Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices....Pages 575-584
Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems....Pages 585-594
Networks on Chip as Hardware Components of an OS for Reconfigurable Systems....Pages 595-605
A Reconfigurable Platform for Real-Time Embedded Video Image Processing....Pages 606-615
Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits....Pages 616-626
HW-Driven Emulation with Automatic Interface Generation....Pages 627-637
Implementation of HW$im – A Real-Time Configurable Cache Simulator....Pages 638-647
The Bank Nth Chance Replacement Policy for FPGA-Based CAMs....Pages 648-660
Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems....Pages 661-669
A New Arithmetic Unit in GF(2 m ) for Reconfigurable Hardware Implementation....Pages 670-680
A Dynamic Routing Algorithm for a Bio-inspired Reconfigurable Circuit....Pages 681-690
An FPL Bioinspired Visual Encoding System to Stimulate Cortical Neurons in Real-Time....Pages 691-700
Power Analysis of FPGAs: How Practical Is the Attack?....Pages 701-710
A Power-Scalable Motion Estimation Architecture for Energy Constrained Applications....Pages 712-721
A Novel Approach for Architectural Models Characterization. An Example through the Systolic Ring....Pages 722-732
A Generic Architecture for Integrated Smart Transducers....Pages 733-744
Customisable Core-Based Architectures for Real-Time Motion Estimation on FPGAs....Pages 745-754
A High Speed Computation System for 3D FCHC Lattice Gas Model with FPGA....Pages 755-765
Implementation of ReCSiP: A ReConfigurable Cell SImulation Platform....Pages 766-775
On the Implementation of a Margolus Neighborhood Cellular Automata on FPGA....Pages 776-785
Fast Modular Division for Application in ECC on Reconfigurable Logic....Pages 786-795
Non-uniform Segmentation for Hardware Function Evaluation....Pages 796-807
A Dual-Path Logarithmic Number System Addition/Subtraction Scheme for FPGA....Pages 808-817
A Modular Reconfigurable Architecture for Efficient Fault Simulation in Digital Circuits....Pages 818-827
Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices....Pages 828-838
Fault Simulation Using Partially Reconfigurable Hardware....Pages 839-848
Switch Level Fault Emulation....Pages 849-858
An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall....Pages 859-868
IPsec-Protected Transport of HDTV over IP....Pages 869-879
Fast, Large-Scale String Match for a 10Gbps FPGA-Based Network Intrusion Detection System....Pages 880-889
Irregular Reconfigurable CAM Structures for Firewall Applications....Pages 890-899
Compiling for the Molen Programming Paradigm....Pages 900-910
Laura: Leiden Architecture Research and Exploration Tool....Pages 911-920
Communication Costs Driven Design Space Exploration for Reconfigurable Architectures....Pages 921-933
From Algorithm Graph Specification to Automatic Synthesis of FPGA Circuit: A Seamless Flow of Graphs Transformations....Pages 934-943
Adaptive Real-Time Systems and the FPAA....Pages 944-947
Challenges and Successes in Space Based Reconfigurable Computing....Pages 948-951
Adaptive Processor: A Dynamically Reconfiguration Technology for Stream Processing....Pages 952-955
Efficient Reconfigurable Logic Circuits for Matching Complex Network Intrusion Detection Patterns....Pages 956-959
FPGAs for High Accuracy Clock Synchronization over Ethernet Networks....Pages 960-963
Project of IPv6 Router with FPGA Hardware Accelerator....Pages 964-967
A TCP/IP Based Multi-device Programming Circuit....Pages 968-971
Design Flow for Efficient FPGA Reconfiguration....Pages 972-975
High-Level Design Tools for FPGA-Based Combinatorial Accelerators....Pages 976-979
Using System Generator to Design a Reconfigurable Video Encryption System....Pages 980-983
MATLAB/Simulink Based Methodology for Rapid-FPGA-Prototyping....Pages 984-987
DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems....Pages 988-991
FPGA Implementation of a Maze Routing Accelerator....Pages 992-995
Model Checking Reconfigurable Processor Configurations for Safety Properties....Pages 996-999
A Statistical Analysis Tool for FPLD Architectures....Pages 1000-1003
FPGA-Implementation of Signal Processing Algorithms for Video Based Industrial Safety Applications....Pages 1004-1007
Configurable Hardware Architecture for Real-Time Window-Based Image Processing....Pages 1008-1011
An FPGA-Based Image Connected Component Labeller....Pages 1012-1015
FPGA Implementation of Adaptive Non-linear Predictors for Video Compression....Pages 1016-1019
Reconfigurable Systems in Education....Pages 1020-1023
Data Dependent Circuit Design: A Case Study....Pages 1024-1027
Design of a Power Conscious, Customizable CDMA Receiver....Pages 1028-1031
Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms....Pages 1032-1035
A VHDL Library to Analyse Fault Tolerant Techniques....Pages 1036-1039
Hardware Design with a Scripting Language....Pages 1040-1043
Testable Clock Routing Architecture for Field Programmable Gate Arrays....Pages 1044-1047
FPGA Implementation of Multi-layer Perceptrons for Speech Recognition....Pages 1048-1052
FPGA Based High Density Spiking Neural Network Array....Pages 1053-1056
FPGA-Based Computation of Free-Form Deformations....Pages 1057-1061
FPGA Implementations of Neural Networks – A Survey of a Decade of Progress....Pages 1062-1066
FPGA-Based Hardware/Software CoDesign of an Expert System Shell....Pages 1067-1070
Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System....Pages 1071-1074
Hardware-Software Codesign in Embedded Asymmetric Cryptography Application – A Case Study....Pages 1075-1078
On-chip and Off-chip Real-Time Debugging for Remotely-Accessed Embedded Programmable Systems....Pages 1079-1082
Fast Region Labeling on the Reconfigurable Platform ACE-V....Pages 1083-1086
Modified Fuzzy C-Means Clustering Algorithm for Real-Time Applications....Pages 1087-1090
Reconfigurable Hybrid Architecture for Web Applications....Pages 1091-1094
FPGA Implementation of the Adaptive Lattice Filter....Pages 1095-1098
Specifying Control Logic for DSP Applications in FPGAs....Pages 1099-1102
FPGA Processor for Real-Time Optical Flow Computation....Pages 1103-1106
A Data Acquisition Reconfigurable Coprocessor for Virtual Instrumentation Applications....Pages 1107-1110
Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures....Pages 1111-1114
A Controlled Data-Path Allocation Model for Dynamic Run-Time Reconfiguration of FPGA Devices....Pages 1115-1118
Architecture Template and Design Flow to Support Application Parallelism on Reconfigurable Platforms....Pages 1119-1122
Efficient Implementation of the Singular Value Decomposition on a Reconfigurable System....Pages 1123-1126
A New Reconfigurable-Oriented Method for Canonical Basis Multiplication over a Class of Finite Fields GF(2 m )....Pages 1127-1130
A Study on the Design of Floating-Point Functions in FPGAs....Pages 1131-1134
Design and Implementation of RNS-Based Adaptive Filters....Pages 1135-1138
Domain-Specific Reconfigurable Array for Distributed Arithmetic....Pages 1139-1144
Design and Implementation of Priority Queuing Mechanism on FPGA Using Concurrent Periodic EFSMs and Parametric Model Checking....Pages 1145-1148
Custom Tag Computation Circuit for a 10Gbps SCFQ Scheduler....Pages 1149-1152
Exploiting Stateful Inspection of Network Security in Reconfigurable Hardware....Pages 1153-1157
Propose of a Hardware Implementation for Fingerprint Systems....Pages 1158-1161
APPLES: A Full Gate-Timing FPGA-Based Hardware Simulator....Pages 1162-1165
Designing, Scheduling, and Allocating Flexible Arithmetic Components....Pages 1166-1169
UNSHADES-1: An Advanced Tool for In-System Run-Time Hardware Debugging....Pages 1170-1173
Back Matter....Pages -