Fault Tolerant Computer Architecture

Fault Tolerant Computer  Architecture......Page 2
Synthesis Lectures on Computer  Architecture......Page 4
Keywords......Page 7
Dedication......Page 8
Acknowledgments......Page 9
Contents......Page 10
1.1   GOALS OF THIS BOOK......Page 14
1.2.1 Masking......Page 15
1.2.3 Underlying Physical Phenomena......Page 16
1.3.1 Smaller Devices and Hotter Chips......Page 18
1.3.3 More Complicated Designs......Page 19
1.4.1 Error Type......Page 20
1.4.3 Number of Simultaneous Errors......Page 21
1.5.1 Availability......Page 22
1.5.5 Failures in Time......Page 23
1.5.6 Architectural Vulnerability Factor......Page 24
1.6 THE REST OF THIS BOOK......Page 25
1.7 REFERENCES......Page 26
2.1.1 Physical Redundancy......Page 32
2.1.3 Information Redundancy......Page 35
2.1.4  The End-to-End Argument......Page 38
2.2.1  Functional Units......Page 40
2.2.3 Tightly Lockstepped Redundant Cores......Page 42
2.2.4 Redundant Multithreading Without Lockstepping......Page 43
2.2.5  Dynamic Verification of Invariants......Page 47
2.2.6 High-Level Anomaly Detection......Page 52
2.2.7 Using Software to Detect Hardware Errors......Page 54
2.2.8  Error Detection Tailored to Specific Fault Models......Page 55
2.3.1 Error Code Implementation......Page 57
2.3.2 Beyond EDCs......Page 58
2.3.3 Detecting Errors in Content Addressable Memories......Page 59
2.3.4  Detecting Errors in Addressing......Page 60
2.4 MULTIPROCESSOR MEMORY SYSTEMS......Page 61
2.4.1 Dynamic Verification of Cache Coherence......Page 62
2.4.2  Dynamic Verification of Memory Consistency......Page 63
2.6 REFERENCES......Page 65
3.1.1 Forward Error Recovery......Page 74
3.1.2 Backward Error Recovery......Page 75
3.1.3  Comparing the Performance of FER and BER......Page 81
3.2.2 BER for Cores......Page 82
3.3.1 FER for Caches and Memory......Page 84
3.3.2 BER for Caches and Memory......Page 85
3.4 ISSUES UNIQUE TO MULTIPROCESSORS......Page 86
3.4.2 Which Algorithm to Use for Saving the Recovery Point......Page 87
3.5 SOFTWARE-IMPLEMENTED BER......Page 88
3.6 CONCLUSIONS......Page 89
3.7 REFERENCES......Page 90
4.1.1 The Benefits of Diagnosis......Page 94
4.1.2 System Model Implications......Page 95
4.2.1 Using Periodic BIST......Page 96
4.2.2 Diagnosing During Normal Execution......Page 97
4.4 MULTIPROCESSORS......Page 98
4.6 REFERENCES......Page 99
5.1 GENERAL CONCEPTS......Page 102
5.2.1 Superscalar Cores......Page 103
5.3 CACHES AND MEMORY......Page 104
5.4.2  Using the Scheduler to Hide Faulty Functional Units......Page 105
5.4.3 Sharing Resources Across Cores......Page 106
5.4.4 Self-Repair of Noncore Components......Page 107
5.6 REFERENCES......Page 108
6.1 ADOPTION BY INDUSTRY......Page 112
6.2.4 Fault Vulnerability Reduction......Page 113
6.3 REFERENCES......Page 114
Author Biography......Page 116