Essentials of Computer Architecture

Cover\0\0\0\0\0\0\0\0\0\0\0\0......Page 1
Title Page......Page 4
Copyright......Page 5
Contents......Page 8
Preface......Page 22
1.2 Learning The Essentials......Page 26
1.3 Organization Of The Text......Page 27
1.6 Summary......Page 28
PART I: Basics......Page 30
2.2 Electrical Terminology: Voltage And Current......Page 32
2.3 The Transistor......Page 33
2.4 Logic Gates......Page 34
2.5 Symbols Used For Gates......Page 35
2.6 Construction Of Gates From Transistors......Page 36
2.7 Example Interconnection Of Gates......Page 37
2.8 Multiple Gates Per Integrated Circuit......Page 39
2.10 Circuits That Maintain State......Page 40
2.11 Transition Diagrams......Page 41
2.12 Binary Counters......Page 42
2.13 Clocks And Sequences......Page 43
2.14 The Important Concept Of Feedback......Page 45
2.16 Iteration In Software Vs. Replication In Hardware......Page 47
2.17 Gate And Chip Minimization......Page 48
2.19 Power Distribution And Heat Dissipation......Page 49
2.20 Timing......Page 50
2.21 Physical Size And Process Technologies......Page 51
2.23 Levels Of Abstraction......Page 52
2.24 Summary......Page 53
3.2 Digital Logic And Abstraction......Page 54
3.4 Byte Size And Possible Values......Page 55
3.5 Binary Arithmetic......Page 56
3.6 Hexadecimal Notation......Page 57
3.7 Notation For Hexadecimal And Binary Constants......Page 58
3.8 Character Sets......Page 59
3.10 Unsigned Integers, Overflow, And Underflow......Page 60
3.11 Numbering Bits And Bytes......Page 61
3.12 Signed Integers......Page 62
3.13 An Example Of Two’s Complement Numbers......Page 63
3.14 Sign Extension......Page 64
3.15 Floating Point......Page 65
3.18 Data Aggregates......Page 67
3.20 Summary......Page 68
PART II: Processors......Page 70
4.2 Von Neumann Architecture......Page 72
4.4 The Range Of Processors......Page 73
4.5 Hierarchical Structure And Computational Engines......Page 74
4.6 Structure Of A Conventional Processor......Page 76
4.8 Processor Categories And Roles......Page 77
4.10 Stored Programs......Page 79
4.11 The Fetch-Execute Cycle......Page 80
4.12 Clock Rate And Instruction Rate......Page 81
4.14 Starting The Fetch-Execute Cycle......Page 82
4.15 Summary......Page 83
5.2 Mathematical Power, Convenience, And Cost......Page 86
5.3 Instruction Set And Representation......Page 87
5.6 Variable-Length Vs. Fixed-Length Instructions......Page 88
5.7 General-Purpose Registers......Page 89
5.9 Programming With Registers......Page 90
5.10 Register Banks......Page 91
5.11 Complex And Reduced Instruction Sets......Page 92
5.12 RISC Design And The Execution Pipeline......Page 93
5.13 Pipelines And Instruction Stalls......Page 94
5.15 Consequences For Programmers......Page 96
5.17 Forwarding......Page 97
5.19 Program Counter, Fetch-Execute, And Branching......Page 98
5.20 Subroutine Calls, Arguments, And Register Windows......Page 100
5.21 An Example Instruction Set......Page 101
5.22 Minimalistic Instruction Set......Page 103
5.23 The Principle Of Orthogonality......Page 104
5.25 Summary......Page 105
6.2 Zero, One, Two, Or Three Address Designs......Page 108
6.3 Zero Operands Per Instruction......Page 109
6.5 Two Operands Per Instruction......Page 110
6.7 Operand Sources And Immediate Values......Page 111
6.8 The Von Neumann Bottleneck......Page 112
6.9 Explicit And Implicit Operand Encoding......Page 113
6.10 Operands That Combine Multiple Values......Page 114
6.11 Tradeoffs In The Choice Of Operands......Page 115
6.12 Values In Memory And Indirect Reference......Page 116
6.13 Operand Addressing Modes......Page 117
6.14 Summary......Page 118
7.2 A Central Processor......Page 120
7.3 CPU Complexity......Page 121
7.5 Backward Compatibility......Page 122
7.6 Changing Modes......Page 123
7.8 Multiple Levels Of Protection......Page 124
7.9 Microcoded Instructions......Page 125
7.11 The Advantage Of Microcode......Page 127
7.13 Vertical Microcode......Page 128
7.14 Horizontal Microcode......Page 129
7.15 Example Horizontal Microcode......Page 130
7.16 A Horizontal Microcode Example......Page 132
7.17 Operations That Require Multiple Cycles......Page 133
7.18 Horizontal Microcode And Parallel Execution......Page 134
7.19 Look-Ahead And High Performance Execution......Page 135
7.21 Out-Of-Order Instruction Execution......Page 136
7.22 Conditional Branches And Branch Prediction......Page 137
7.24 Summary......Page 138
8.2 Characteristics Of A High-level Programming Language......Page 140
8.3 Characteristics Of A Low-Level Programming Language......Page 141
8.4 Assembly Language......Page 142
8.5 Assembly Language Syntax And Opcodes......Page 143
8.6 Operand Order......Page 145
8.7 Register Names......Page 146
8.9 Assembly Language Programming Paradigm And Idioms......Page 147
8.10 Assembly Code For Conditional Execution......Page 148
8.12 Assembly Code For Definite Iteration......Page 149
8.14 Assembly Code For Procedure Invocation......Page 150
8.15 Assembly Code For Parameterized Procedure Invocation......Page 151
8.16 Consequence For Programmers......Page 152
8.18 Interaction Between Assembly And High-Level Languages......Page 153
8.19 Assembly Code For Variables And Storage......Page 154
8.20 Two-Pass Assembler......Page 155
8.21 Assembly Language Macros......Page 156
8.22 Summary......Page 159
PART III: Memories......Page 160
9.2 Definition......Page 162
9.4 Characteristics Of Memory Technologies......Page 163
9.6 Instruction And Data Store......Page 165
9.8 Summary......Page 166
10.2 Characteristics Of Computer Memory......Page 168
10.3 Static And Dynamic RAM Technologies......Page 169
10.4 Measures Of Memory Technology......Page 170
10.7 Latency And Memory Controllers......Page 171
10.8 Synchronized Memory Technologies......Page 172
10.11 Memory Organization......Page 173
10.12 Memory Access And Memory Bus......Page 174
10.15 Physical Memory Operations......Page 175
10.17 An Extreme Case: Byte Addressing......Page 176
10.18 Byte Addressing With Word Transfers......Page 177
10.19 Using Powers Of Two......Page 178
10.21 Memory Size And Address Space......Page 179
10.23 Measures Of Memory Size......Page 180
10.25 A Memory Dump......Page 181
10.27 Memory Banks And Interleaving......Page 183
10.28 Content Addressable Memory......Page 184
10.30 Summary......Page 185
11.2 Definition......Page 188
11.5 An Interface To Multiple Physical Memory Systems......Page 189
11.6 Address Translation Or Address Mapping......Page 191
11.7 Avoiding Arithmetic Calculation......Page 192
11.8 Discontiguous Address Spaces......Page 193
11.10 Motivation For Virtual Memory......Page 194
11.11 Multiple Virtual Spaces And Multiprogramming......Page 195
11.13 Creating Virtual Spaces Dynamically......Page 196
11.15 Changing The Virtual Space......Page 197
11.16 Virtual Memory, Base-Bound, And Protection......Page 198
11.17 Segmentation......Page 199
11.19 Hardware And Software For Demand Paging......Page 200
11.21 Paging Terminology And Data Structures......Page 201
11.22 Address Translation In A Paging System......Page 202
11.23 Using Powers Of Two......Page 203
11.24 Presence, Use, And Modified Bits......Page 204
11.25 Page Table Storage......Page 205
11.26 Paging Efficiency And A Translation Lookaside Buffer......Page 206
11.27 Consequences For Programmers......Page 207
11.28 Summary......Page 208
12.2 Definition......Page 210
12.3 Characteristics Of A Cache......Page 211
12.4 The Importance Of Caching......Page 212
12.6 Cache Terminology......Page 213
12.7 Best And Worst Case Cache Performance......Page 214
12.9 Cache Replacement Policy......Page 215
12.11 Multi-level Cache Hierarchy......Page 216
12.13 Caches Used With Memory......Page 217
12.15 Demand Paging As A Form Of Caching......Page 218
12.17 Write Through And Write Back......Page 219
12.18 Cache Coherence......Page 220
12.19 L1, L2, and L3 Caches......Page 221
12.21 Instruction And Data Caches......Page 222
12.22 Virtual Memory Caching And A Cache Flush......Page 223
12.23 Implementation Of Memory Caching......Page 224
12.24 Direct Mapping Memory Cache......Page 225
12.25 Using Powers Of Two For Efficiency......Page 226
12.26 Set Associative Memory Cache......Page 227
12.27 Consequences For Programmers......Page 228
12.28 Summary......Page 229
PART IV: I/O......Page 230
13.2 Input And Output Devices......Page 232
13.3 Control Of An External Device......Page 233
13.5 Serial And Parallel Data Transfers......Page 234
13.7 Full-Duplex And Half-Duplex Interaction......Page 235
13.9 The Fundamental Idea Of Multiplexing......Page 236
13.10 Multiple Devices Per External Interface......Page 237
13.12 Summary......Page 238
14.2 Definition Of A Bus......Page 240
14.4 Proprietary And Standardized Buses......Page 241
14.8 Physical Connections......Page 242
14.9 Bus Interface......Page 243
14.10 Address, Control, And Data Lines......Page 244
14.13 The Width Of A Bus......Page 245
14.14 Multiplexing......Page 246
14.15 Bus Width And Size Of Data Items......Page 247
14.16 Bus Address Space......Page 248
14.17 Potential Errors......Page 249
14.18 Address Configuration And Sockets......Page 250
14.21 An Example Of Device Control Using Fetch-Store......Page 251
14.22 Operation Of An Interface......Page 252
14.24 Unified Memory And Device Addressing......Page 253
14.26 Address Map......Page 255
14.27 Program Interface To A Bus......Page 256
14.29 Main And Auxiliary Buses......Page 257
14.31 Switching Fabrics......Page 259
14.32 Summary......Page 260
15.2 I/O Paradigms......Page 262
15.4 Synchronization......Page 263
15.6 Code For Polling......Page 264
15.8 Processor Use And Polling......Page 266
15.10 Interrupt-Driven I/O......Page 267
15.12 Interrupts And The Fetch-Execute Cycle......Page 268
15.13 Handling An Interrupt......Page 269
15.14 Interrupt Vectors......Page 270
15.17 Multiple Levels Of Interrupts......Page 271
15.18 Assignment Of Interrupt Vectors And Priorities......Page 272
15.19 Dynamic Bus Connections And Pluggable Devices......Page 273
15.21 Smart Devices And Improved I/O Performance......Page 274
15.22 Direct Memory Access (DMA)......Page 275
15.23 Buffer Chaining......Page 276
15.25 Operation Chaining......Page 277
15.26 Summary......Page 278
16.1 Introduction......Page 280
16.3 Device Independence, Encapsulation, And Hiding......Page 281
16.4 Conceptual Parts Of A Device Driver......Page 282
16.6 Example Flow Through A Device Driver......Page 283
16.7 Queued Output Operations......Page 284
16.9 Queued Input Operations......Page 286
16.10 Devices That Support Bi-Directional Transfer......Page 287
16.11 Asynchronous Vs. Synchronous Programming Paradigm......Page 288
16.13 I/O As Viewed By An Application......Page 289
16.14 Run-Time I/O Libraries......Page 290
16.15 The Library/Operating System Dichotomy......Page 291
16.16 I/O Operations The OS Supports......Page 292
16.18 Reducing The System Call Overhead......Page 293
16.19 The Important Concept Of Buffering......Page 294
16.20 Implementation of Buffering......Page 295
16.21 Flushing A Buffer......Page 296
16.23 Effectiveness Of Buffering......Page 297
16.24 Buffering In An Operating System......Page 298
16.27 Summary......Page 299
PART V: Advanced Topics......Page 302
17.2 Parallel And Pipelined Architectures......Page 304
17.4 Microscopic Vs. Macroscopic......Page 305
17.6 Examples Of Macroscopic Parallelism......Page 306
17.8 Fine-grain Vs. Coarse-grain Parallelism......Page 307
17.11 Types Of Parallel Architectures (Flynn Classification)......Page 308
17.13 Single Instruction Multiple Data (SIMD)......Page 309
17.14 Multiple Instructions Multiple Data (MIMD)......Page 311
17.15 Communication, Coordination, And Contention......Page 313
17.16 Performance Of Multiprocessors......Page 315
17.17 Consequences For Programmers......Page 317
17.18 Redundant Parallel Architectures......Page 319
17.19 Distributed And Cluster Computers......Page 320
17.20 Summary......Page 321
18.2 The Concept Of Pipelining......Page 324
18.3 Software Pipelining......Page 326
18.4 Software Pipeline Performance And Overhead......Page 327
18.6 How Hardware Pipelining Increases Performance......Page 328
18.7 When Pipelining Can Be Used......Page 331
18.9 Pipeline Architectures......Page 332
18.11 Definition Of Superpipeline Architecture......Page 333
18.12 Summary......Page 334
19.2 Measuring Power And Performance......Page 336
19.3 Measures Of Computational Power......Page 337
19.4 Application Specific Instruction Counts......Page 338
19.5 Instruction Mix......Page 339
19.6 Standardized Benchmarks......Page 340
19.8 Boundary Between Hardware And Software......Page 341
19.10 Amdahl’s Law And Parallel Systems......Page 342
19.11 Summary......Page 343
20.2 Architectural Levels......Page 344
20.3 System-Level Architecture: A Personal Computer......Page 345
20.4 Bus Interconnection And Bridging......Page 346
20.5 Controller Chips And Physical Architecture......Page 347
20.6 Virtual Buses......Page 348
20.9 Board-Level Architecture......Page 350
20.10 Chip-Level Architecture......Page 352
20.11 Structure Of Functional Units On A Chip......Page 353
20.13 Hierarchy Beyond Computer Architectures......Page 354
A1.1 Introduction......Page 356
A1.3 Solderless Breadboard......Page 357
A1.4 Using A Solderless Breadboard......Page 358
A1.6 Power And Ground Connections......Page 359
A1.7 Lab Exercises......Page 360
1 Introduction and account configuration......Page 362
2 Digital Logic: Use of a breadboard......Page 364
3 Digital Logic: Building an adder from gates......Page 366
4 Digital Logic: Clocks and demultiplexing......Page 368
5 Representation: Testing big endian vs. little endian......Page 370
6 Representation: A hex dump program in C......Page 372
7 Processors: Learn a RISC assembly language......Page 374
8 Processors: Function that can be called from C......Page 376
9 Memory: row-major and column-major array storage......Page 378
10 Input / Output: a buffered I/O library......Page 380
11 A hex dump program in assembly language......Page 382
Bibliography......Page 384
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