Engineering the Complex SOC: Fast, Flexible Design with Configurable Processors

Cover......Page 1
Contents......Page 8
List of Figures......Page 16
Foreword......Page 22
Foreword......Page 26
Author’s Preface......Page 28
Acknowledgments......Page 32
 1.1 The Age of Megagate SOCs......Page 34
  1.1.1 Moore’s Law Means Opportunity and Crisis......Page 36
  1.1.2 Roadblock 1: Building the Wrong Chip......Page 37
  1.1.3 Roadblock 2: Building the Chip Wrong......Page 38
  1.2.1 A New SOC for Every System is a Bad Idea......Page 39
  1.2.2 SOC Design Reform: Lower Design Cost and Greater Design Flexibility......Page 40
  1.2.3 Concurrency......Page 41
  1.2.5 Programmability Versus Efficiency......Page 43
  1.2.6 The Key to SOC Design Success: Domain-Specific Flexibility......Page 47
 1.3 What’s Wrong with Today’s Approach to SOC Design?......Page 48
  1.3.1 What’s Wrong with Traditional Processors?......Page 49
  1.3.2 What’s Wrong with Traditional SOC Methodology?......Page 51
  1.4.1 The SOC Design Flow......Page 54
  1.4.2 Configurable Processor as Building Block......Page 55
  1.4.3 A Trivial Example......Page 57
  1.4.4 Results of Application-Specific Processor Configuration......Page 58
  1.4.5 The Processor as SOC Building Block......Page 59
  1.4.6 Solving the System Design Problem......Page 60
  1.4.7 Implications of Improved SOC Methodology......Page 65
  1.4.8 The Transition to Processor-based SOC Design......Page 66
 1.5 Further Reading......Page 67
 2.1 Hardware System Structure......Page 69
  2.1.1 How Is RTL Used Today?......Page 70
  2.1.2 Control, Data Path, and Memory......Page 71
  2.1.3 Hardware Trends......Page 73
 2.2 Software Structure......Page 74
 2.3 Current SOC Design Flow......Page 77
 2.4 The Impact of Semiconductor Economics......Page 81
  2.5.2 Inadequate Product Volume and Longevity......Page 83
  2.5.3 Inflexibility in the Semiconductor Supply Chain......Page 84
  2.5.4 Inadequate Performance, Efficiency, and Cost......Page 85
  2.5.5 Risk, Cost, and Delay in Design and Verification......Page 86
  2.5.7 Solving the Six Problems......Page 87
 2.6 Further Reading......Page 88
Chapter 3 A New Look at SOC Design......Page 89
  3.1.1 Processor Generation......Page 90
  3.2.1 The Evolution of Generic Processors......Page 95
  3.2.3 Processor Extensibility......Page 97
  3.2.4 Designer-Defined Instruction Sets......Page 99
  3.2.5 Memory Systems and Configurability......Page 100
  3.2.6 The Origins of Configurable Processors......Page 102
 3.3 Example: Tensilica Xtensa Processors for EEMBC Benchmarks......Page 103
  3.3.2 Telecommunications......Page 104
  3.3.3 EEMBC Networking Benchmarks......Page 106
  3.3.4 The Processor as RTL Alternative......Page 107
 3.4 System Design with Multiple Processors......Page 111
  3.4.1 Available Concurrency......Page 112
  3.4.2 Parallelism and Power......Page 113
  3.4.4 Forms of Partitioning......Page 114
  3.4.5 Processor Interface and Interconnect......Page 117
 3.5 New Essentials of SOC Design Methodology......Page 122
  3.5.1 SOC Design Flow......Page 123
  3.5.2 The Essential Phases of the New Flow......Page 125
 3.6 Addressing the Six Problems......Page 126
  3.6.2 Build an Optimized Platform to Aggregate Volume......Page 127
  3.6.5 Replace Hard-wired Design with Tuned Processors......Page 128
 3.7 Further Reading......Page 129
Chapter 4 System-Level Design of Complex SOCs......Page 132
 4.1 Complex SOC System Architecture Opportunities......Page 134
  4.1.1 The Basic Process of Parallel Design......Page 135
  4.1.2 The SOC as a Network of Interacting Components......Page 136
  4.1.3 Impact of Silicon Scaling on System Partitioning......Page 138
  4.1.4 Why Multiple Processors......Page 139
  4.1.5 Types of Concurrency and System Architecture......Page 140
  4.1.6 Latency, Bandwidth and Communications Structure......Page 143
  4.1.7 Reliability and Scalability in SOC Communications Architecture......Page 149
  4.1.8 Communications Programming Flexibility......Page 151
  4.1.9 Early vs. Late-Binding of Interaction Mechanisms......Page 153
 4.2 Major Decisions in Processor-Centric SOC Organization......Page 155
  4.2.1 The Starting Point: Essential Interfaces and Computation......Page 156
  4.2.2 Parallelizing a Task......Page 159
  4.2.3 Assigning Tasks to Processors......Page 161
  4.2.4 Choosing the Right Communications Structure......Page 166
  4.3.1 Software Communication Modes......Page 171
  4.3.2 Message Passing......Page 172
  4.3.3 Shared Memory......Page 174
  4.3.4 Device Driver......Page 177
 4.4 Hardware Interconnect Mechanisms......Page 178
  4.4.1 Buses......Page 179
  4.4.2 Direct Connect Ports......Page 183
  4.4.3 Data Queues......Page 185
 4.5 Performance-Driven Communication Design......Page 188
  4.5.2 System Modeling Languages......Page 190
  4.5.3 System Modeling Example: XTMP......Page 192
  4.5.4 Balancing Computation and Communications......Page 198
  4.6.1 Recommended Design Flow......Page 199
  4.6.2 Shifts in SOC Design Methodology......Page 201
  4.7.1 Memories......Page 203
  4.7.2 I/O Peripherals......Page 205
  4.7.3 Hardwired Logic Blocks......Page 206
 4.8 Implications of Processor-Centric SOC Architecture......Page 207
 4.9 Further Reading......Page 209
Chapter 5 Configurable Processors: A Software View......Page 211
  5.1.1 Applications, Programming Languages, and Processor Architecture......Page 213
  5.1.2 A Quick Example: Pixel Blending......Page 215
  5.2.1 Profiling and Performance......Page 217
 5.3 The Basics of Instruction Extension......Page 223
  5.3.1 Instruction Extension Methods......Page 226
  5.3.2 Upgrading the Application......Page 231
  5.3.3 The Tradeoff between Instruction-Set Performance and Generality......Page 234
  5.3.4 Operation Fusion......Page 235
  5.3.5 Compound Operations......Page 242
  5.3.6 SIMD Instructions......Page 244
  5.4.1 The Base User Instruction Set......Page 247
  5.4.2 The Application-Specific Instruction Set......Page 251
  5.4.3 The System-Programming Instruction Set......Page 252
 5.5 Processor Performance Factors......Page 254
  5.5.1 The Software Development Environment......Page 259
  5.5.2 The Software Runtime Environment......Page 266
 5.6 Example: Tuning a Large Task......Page 269
  5.7.1 Basic Memory-System Strategy......Page 276
  5.7.2 Detailed Memory-System Tuning......Page 277
  5.7.3 Aggregate Memory System Performance......Page 278
  5.7.4 Inner-Loop Data-Reference Tuning......Page 281
 5.8 Long Instruction Words......Page 286
  5.8.1 Code Size and Long Instructions......Page 288
  5.8.2 Long Instruction Words and Automatic Processor Generation......Page 290
 5.9 Fully Automatic Instruction-Set Extension......Page 293
 5.10 Further Reading......Page 299
Chapter 6 Configurable Processors: A Hardware View......Page 300
 6.1 Application Acceleration: A Common Problem......Page 301
 6.2 Introduction to Pipelines and Processors......Page 304
  6.2.2 RISC Pipeline Basics......Page 305
  6.2.3 Pipelines for Extended Instruction-Set Implementation......Page 307
  6.2.4 Guarantee of Correctness in Processor Hardware Extension......Page 308
 6.3 Hardware Blocks to Processors......Page 309
  6.3.1 The Basic Transformation of Hardware into Instructions......Page 310
  6.3.2 One Primitive Operation per Instruction......Page 313
  6.3.3 Multiple Independent Operations per Instruction......Page 318
  6.3.4 Pipelined Instruction......Page 321
  6.3.5 Tradeoffs in Mapping Hardware Functions to Processor Instructions......Page 323
 6.4 Moving from Hardwired Engines to Processors......Page 324
  6.4.1 Translating Finite-State Machines to Software......Page 325
  6.4.2 Designing Application-Specific Processors for Flexibility......Page 329
  6.4.3 Moving from Microcoded Engines to Processors......Page 331
  6.4.4 Microcode Data Paths......Page 335
  6.4.5 Encoding Operations......Page 337
  6.4.6 Microprograms......Page 340
 6.5 Designing the Processor Interface......Page 341
  6.5.1 Memory-Mapped RAM......Page 344
  6.5.2 Memory-Mapped Queues and Registers......Page 347
  6.5.3 Wire-Based Input and Output......Page 352
 6.6 A Short Example: ATM Packet Segmentation and Reassembly......Page 356
  6.7.1 The Deeply Buried Task Engine......Page 361
  6.7.2 Designing with Spare Processors......Page 363
  6.7.3 The System-Monitor Processor......Page 365
  6.8.1 Hardware Flow......Page 366
  6.8.2 Verification Flow......Page 369
 6.9 Progress in Hardware Abstraction......Page 372
 6.10 Further Reading......Page 373
 7.1 Pipelining for Processor Performance......Page 375
 7.2 Inside Processor Pipeline Stalls......Page 379
  7.2.2 Pipelines and Exceptions......Page 383
  7.2.3 Alternative Pipelining for Complex Instructions......Page 385
  7.3.1 Overcoming Differences in Branch Architecture......Page 387
  7.3.2 Overcoming Limitations in Memory Access......Page 392
  7.4.1 MP Debug......Page 394
  7.4.2 MP Trace......Page 396
  7.5.1 Pipelining with Multiple Memory Ports......Page 398
  7.5.2 Memory Alignment in SIMD Instruction Sets......Page 399
  7.5.3 Synchronization Mechanisms for Shared Memory......Page 400
 7.6 Optimizing Power Dissipation in Extensible Processors......Page 405
  7.6.2 Impact of Extensibility on Performance......Page 406
  7.6.3 Memory Power......Page 408
 7.7 Essentials of TIE......Page 410
  7.7.1 TIE Operations......Page 413
  7.7.2 TIE States and Register Files......Page 415
  7.7.3 External TIE Ports and Queues......Page 416
  7.7.4 TIE Constants......Page 418
  7.7.6 Using Built-in Registers, Interfaces, and Functions with TIE......Page 420
  7.7.7 Shared and Iterative TIE Functions......Page 423
  7.7.8 Multi-Slot Instructions......Page 424
 7.8 Further Reading......Page 425
Chapter 8 The Future of SOC Design: The Sea of Processors......Page 427
 8.1 What’s Happening to SOC Design?......Page 428
  8.1.1 SOC and ROI......Page 429
  8.1.2 The Designer’s Dilemma......Page 431
  8.1.3 The Limitations of General-Purpose Processors......Page 432
  8.1.4 The New Processor......Page 434
  8.1.5 What Makes These Processors Different?......Page 436
  8.1.6 The SOC Design Transition......Page 438
 8.2 Why Is Software Programmability So Central?......Page 441
 8.4 Processor Scaling Model......Page 443
  8.4.1 Summary of Model Assumptions......Page 450
 8.5 Future Applications of Complex SOCs......Page 452
 8.6 The Future of the Complex SOC Design Process......Page 454
 8.7 The Future of the Industry......Page 460
 8.8 The Disruptive-Technology View......Page 464
 8.9 The Long View......Page 469
 8.10 Further Reading......Page 470
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