Emerging Electronic Devices, Circuits and Systems: Select Proceedings of EEDCS Workshop Held in Conjunction with ISDCS 2022

Contents
About the Editors
Hardware-Efficient Q-Learning Accelerator for Robot Path Planning
	1 Introduction
	2 Deep Reinforcement Learning for Walking Robot
	3 Development of Q-Learning Algorithm for High-Performance Robot Path Planning
	4 Efficient Hardware Architecture in Verilog-HDL
	5 Conclusion
	References
Performance Analysis of Temperature on Wireless Performance for Vertically Stacked Junctionless Nanosheet Field Effect Transistor
	1 Introduction
	2 Device Portraiture and Simulation Setup
	3 Results and Discussion
	4 Conclusion
	References
Analysis of the NH3 Adsorption on Boron-Arsenic Co-doped Monolayer Graphene: A First Principle Study
	1 Introduction
	2 Computational Methodology
	3 Results and Discussion
		3.1 Effects of B/A Co-doping on Structural and Electronic Properties
		3.2 Gas-Molecule Adsorption on Homogenously Doped and Co-doped Graphene Systems
	4 Conclusion
	References
Quantum Fault-Tolerant Implementation of a Majority-Based 4-Bit BCD Adder
	1 Introduction
	2 Preliminaries
		2.1 Quantum Circuits
		2.2 4-Bit BCD Adder
	3 Proposed Methodology
		3.1 Reversible 4-Bit BCD Adder
		3.2 Fault-Tolerant Quantum Implementation of a 4-Bit BCD Adder
	4 Experimental Results
	5 Conclusion
	References
CNTFET-Based Universal Filter Using DO-CCII
	1 Introduction
	2 Overview of CNTFET
	3 Overview of DO-CCII
	4 DO-CCII-Based Universal Biquadratic Filter
	5 Conclusion
	References
Designing of Energy-Efficient XOR Gate Implementing DWM Spintronics
	1 Introduction
	2 Background
		2.1 Magnetic Tunnel Junction
		2.2 Domain Wall Motion
	3 Propound Device Architecture and Working
		3.1 Architecture
		3.2 Working
	4 Results and Discussion
	5 Conclusion
	References
Short-Channel Effects in Independently Controlled MG-MOSFET
	1 Introduction
	2 Origin of SCE in MG-MOSFET
	3 Modeling of SCE in MG-MOSFET
	4 Conclusion
	References
Reduction of Interconnect Delay and Resistance While Minimizing  Grid Area in GNR-Based VLSI  Routing Problem
	1 Introduction
		1.1 Literature Review and Motivation
		1.2 Contribution and Outline of the Work
		1.3 Organization of the Paper
	2 GNR Routing Problem
	3 Problem Formulation
	4 Proposed Method
		4.1 Initial Observations
		4.2 Algorithm for GNR Routing to Reduce the Interconnect Delay and Resistance with Minimized Grid Area
	5 Experimental Result
	6 Conclusion
	References
Modeling of Pristine and Intercalation Doped Multilayer Graphene Nanoribbon Conductors with Energy-per-Layer Screening
	1 Introduction
	2 Effective Conducting Layer
		2.1 Equivalent Single Conductor Model
		2.2 Computation of Effective Number of Layers
	3 Modeling of TC-MLGNR Conductors Based on Fermi Level Screening
	4 Conclusion
	References
Enhancing Lifetime of Non-volatile Memory Caches by Write-Aware Techniques
	1 Introduction
	2 Related Work
	3 Motivation
	4 Write-Aware Last Level Non-volatile Cache
		4.1 LRU-CB Replacement Policy
		4.2 Impact of LRU-CB with Write Distribution
		4.3 Write Distribution in WALL-NVC
	5 Experimental Setup and Result Analysis
		5.1 Performance Analysis
		5.2 Sensitivity Analysis
		5.3 Overhead Analysis
	6 Conclusion
	References
Microfluidic Dilution by Recycling Arbitrary Stock Solutions Using Various Mixing Models
	1 Introduction
	2 Preliminaries of Sample Preparation
	3 Motivation and Problem Formulation
		3.1 Motivation
		3.2 Problem Formulation
	4 Proposed Methodology
	5 Simulation Results
	6 Conclusions
	References
Design and Analysis of Posit Processing Engine with Embedded Activation Functions for Neural Network Applications
	1 Introduction
	2 Related Works
	3 Posit Number System and Processing Engine
		3.1 Posit Number System
		3.2 Generic Processing Engine
	4 Proposed Posit-Based Processing Engine
		4.1 Posit-Based Multiply Accumulate Unit with Quire
		4.2 Posit-Based Activation Module
	5 Experimental Results
	6 Conclusion
	References
Multinet Global Routing Algorithm for On-Chip Optical Interconnects to Minimize Optical Signal Loss
	1 Introduction
	2 Literature Survey
		2.1 Global Routing
		2.2 Optical Interconnect Routing
	3 Problem Formulation
		3.1 Waveguide Curvature Loss
		3.2 Waveguide Crossings
	4 Proposed Methodology
		4.1 Construction of MABZ
		4.2 Construction of SMR and Computation of Waveguide Bend Loss
		4.3 Computation of Waveguide Crossings
	5 Results and Discussion
	6 Conclusion
	References
Performance Enhancement of Dielectric Engineered Doping Less InGaN Tunnel FET for Low Power Analog/Radio Frequency Applications
	1 Introduction
	2 Structures of Devices and the Parameters Used for Simulations
	3 Results and Discussions
	4 Conclusion
	References
Voltammetric Detection and Controlled Inhibition of Decarboxylation of Gallic Acid (GA) in Green Tea Using Eugenol
	1 Introduction
	2 Materials and Methods
		2.1 Sample Procurement and Preparation
		2.2 CV Technique
	3 Experimental Details
		3.1 CV Technique and Its Equivalent Circuit
	4 Results and Discussion
		4.1 Voltammetric Analysis
		4.2 Effect of Settling Time
		4.3 Effect of Boiling Time
		4.4 Effect of Eugenol on the Oxidation of Green Tea
	5 Conclusion
	References
Impact of a Tubular Dielectric Medium on Peak Noise and Crosstalk Delay in a Coaxial TSV
	1 Introduction
	2 TSV Configuration and Equivalent Circuit Model
		2.1 TSV Structure and Physical Parameters
		2.2 Equivalent Electrical Model of a Coaxial TSV
	3 Impact of a Tubular Dielectric Medium on a Coaxial TSV
		3.1 Impact of Tubular Dielectric Medium on Peak Noise
		3.2 Impact of Tubular Dielectric on Crosstalk Induced Delay
	4 Conclusion
	References
Novel Approach for the Reduction of Critical Paths in Static Timing Analysis Without Degradation in QOR
	1 Introduction
	2 Proposed Technique
		2.1 Path Delay Analysis
		2.2 Timing Analysis of a Path and Data Propagation
		2.3 Application-Specific Algorithm
	3 Implementation Methodology
		3.1 Post-synthesis Physical Design Flow
		3.2 Post-layout ECO Timing Fix
	4 Conclusion
	References
Coupling Transition Reduction on On-Chip Buses Using Adaptive Bus Encoding (ABE)
	1 Introduction
	2 Related Work and Their Contributions
	3 Adaptive On-Chip Bus Encoding
		3.1 Mathematical Background
		3.2 Theoretical Description of the Method
	4 Results
		4.1 Impact of Observation Window Size on Coupling Savings
		4.2 Comparison with Pre-existing Encoding Schemes
	5 Conclusion
	References
Modelling and Analysis of Confluence Attack by Hardware Trojan in NoC
	1 Introduction
	2 Related Work
	3 Architecture Details for Baseline TCMP
	4 Threat Model
		4.1 Performance Metrics for Impact Analysis
	5 Experimental Setup and Results
		5.1 Effect of HT on Virtual Channel Utilization
		5.2 Effect of HT on Flits Processing and Flits Deflection Count
		5.3 Effect of HT on Link Utilization
		5.4 Effect of HT on Router Load in Terms of Count of Activation of Each Router of Mesh
		5.5 Effect of HT on Variation in Buffer Reads for Each Router of Mesh
		5.6 Effect of HT on Hop Count, Network Latency, and Queuing Latency
	6 Conclusion and Future Work
	References
Investigating the Impact of Ge-Quantum Well Width in Si/SiO2/Ge/SiO2/Pt Resonant Tunneling Device with NEGF Formalism
	1 Introduction
	2 Scheme of the Device
	3 Theoretical Modeling
	4 Results and Discussion
	5 Conclusion
	References
Comparative Analysis of Normal and Anemic RBC by Employing Impedimetric and Voltammetric Studies
	1 Introduction
	2 Materials and Methods
		2.1 Sample Preparation
		2.2 Theoretical Representation
	3 Experimental Details
		3.1 Electrochemical Measurements
	4 Results and Discussions
		4.1 Voltammetric Analysis
		4.2 EIS Analysis
	5 Conclusion
	References
Differential Fault Analysis of Trivium Using Artificial Neural Network  on SoC Platform
	1 Introduction
	2 Background Studies
		2.1 Basics of Trivium Cipher
		2.2 ANN for Crypt-Analysis
	3 Proposed Method
		3.1 Data Set Generation
		3.2 Parameters Selection
		3.3 Model Training
	4 Hardware Implementation
	5 Result and Performance Analysis
	6 Conclusion and Future Work
	References
Investigation of Adders for Retinal Neuromorphic Circuits
	1 Introduction
	2 Literature Survey
	3 Classical CMOS Analog Adder
		3.1 Circuit Implementation of Classical CMOS Analog Adder
		3.2 Simulation Results of Classical CMOS Analog Adder
	4 Differential Analog Adder
		4.1 Circuit Implementation of Differential Analog Adder
		4.2 Simulation Results of Differential Analog Adder
	5 Low Power Analog Adder
		5.1 Circuit Implementation of Low Power Analog Adder
		5.2 Simulation Results of Low Power Analog Adder
	6 Nonlinear Analog Adder
		6.1 Circuit Implementation of Nonlinear Analog Adder
		6.2 Simulation Results of Nonlinear Analog Adder
	7 Op-Amp-Based Analog Adder
		7.1 Circuit Implementation of Op-Amp-Based Analog Adder
		7.2 Simulation Results of Op-Amp-Based Analog Adder
	8 Application of Adders for Differential Motion Detection
		8.1 Application of Classical CMOS Analog Adder in Starburst Amacrine Cell
		8.2 Application of Op-Amp Adder in Starburst Amacrine Cell
		8.3 Development of Differential Motion Detector with Op-Amp Adder
	9 Conclusion
	References
Sputtered HfO2/ZrO2 Induced Interfacial Ferroelectric HZO Layer for Negative Capacitance Applications
	1 Introduction
	2 Experimental Details
	3 Results and Discussion
	4 Conclusion
	References
Gain Flattening of Erbium-Doped Fiber Amplifier Using an In-Line M-S-M Fiber Structure
	1 Introduction
	2 Theory
	3 Results and Discussion
	References
Experimental Demonstration of Electric Field Sensing Using Sagnac Loop Based Fiber Cantilever Configuration
	1 Introduction
	2 Sagnac Mirror Loop Configuration
		2.1 Experimental Setup
	3 Results Obtained from Our Model
		3.1 Theoretical Model
	4 Conclusion
	References
An SMT-Based Reverse Engineering  of Register Allocation in High-Level Synthesis
	1 Introduction
	2 Related Work
	3 Register to Variable Reverse Engineering Approach
		3.1 FSMDs and Related Theory
	4 SMT-Based Formulation of Register to Variable Reverse Engineering
	5 Experimental Results
	6 Conclusion
	References
Hardware Primitives-Based Accelerator Architecture for NTRU-HRSS Scheme
	1 Introduction
	2 Related Works
	3 NTRU-HRSS—Brief Description
		3.1 NTRU-HRSS Encryption [4]
		3.2 NTRU-HRSS Decryption [4]
	4 Proposed NTRU-HRSS Accelerator Architecture
		4.1 Modular Polynomial Multiplier
	5 Verification of NTRU-HRSS Accelerator
	6 Hardware Implementation and Resources Utilization of NTRU Primitives and NTRU-HRSS Accelerator
		6.1 Polynomial Multipliers for NTRU-HRSS
		6.2 Polynomial Lift for NTRU-HRSS
		6.3 NTRU-HRSS Accelerator–Encryption and Decryption
	7 Conclusions and Future Works
	References
Distributed Agent-Based Voltage Control Approach for Active Distribution Systems
	1 Introduction
	2 Proposed Voltage Control Approach
	3 Mathematical Formulation
		3.1 Voltage Regulators Objective Function
		3.2 Reactive Power Control of the DG Inverter
		3.3 Overall Voltage Control Approach
	4 Simulation Results
		4.1 Case 1: Voltage Control Using Optimal Control Rule
		4.2 Case 2: Voltage Control Using Suboptimal Control Strategy
		4.3 Case 3: Comparison Among Optimal, Suboptimal, and Conventional Control
		4.4 Case 4: Long-Term Simulation
		4.5 Case 5: Overall Control Approach
	5 Conclusions
	References
Application Mapping of Fully Connected 3D NoC Using Latency Prediction Model
	1 Introduction
	2 Previous Work
	3 Analytical Model
	4 LPNet Model for Fully Connected 3D NoCs
	5 Application Mapping
	6 Results and Analyses
		6.1 LPNet Model Performance Analysis
		6.2 Complexity Analysis of DPSO Using Communication Cost and Prediction Model
		6.3 DPSO Using Prediction Model
	7 Conclusion
	References
Smart Device and Mobile Application for Remote Health Monitoring and Alarming
	1 Introduction
	2 Problem Statement
	3 Methodology
	4 Hardware and Software Requirements
		4.1 Hardware Requirements
		4.2 Software Requirements
	5 Future Scope
	6 Conclusion
	References
Designing a Silicon-on-Insulator (SOI) Waveguide with an Aim of Studying Nonlinear Pulse Reshaping
	1 Introduction
	2 Designing a Buried Waveguide Using the Effective Index Method
	3 Nonlinear Pulse Reshaping in the Proposed SOI Buried Waveguide
	4 Conclusion
	References
FaceDig: A Deep Neural Network-Based Fake Image Detection Scheme
	1 Introduction
	2 Methodology
		2.1 Dataset Preparation
		2.2 Architecture of Convolution Neural Network (CNN)
	3 Results and Discussion
		3.1 Dataset Preparation
	4 Conclusion
	References
Self-heating Effects on Power Loss of SiC-Based General-Purpose Inverter-Stack Circuit
	1 Introduction
	2 General-Purpose Inverter-Stack Circuit
	3 Self-heating Effects in GPIS System
	4 Conclusion
	References
A Novel Approach to Model and Analyze Wafer–Wafer Hybrid Bonding
	1 Introduction
	2 Three-Dimensional Integration Using Wafer–Wafer Hybrid Bonding
	3 Model Description
	4 Results and Discussions
	5 Conclusion
	References
Successive Approximation Register Analog-to-Digital Converter—A Tutorial
	1 Introduction
	2 SAR ADC Architectures
		2.1 Binary-Weighted SAR
		2.2 Split SAR
	3 SAR ADC Design Approach
		3.1 Settling Time Consideration
		3.2 Noise Consideration
		3.3 Power Consumption in CDAC
	4 Conclusion
	References
Origin of Hump in Ids for Body-Tied SOI-MOSFET and Its Influence on Circuit Performance
	1 Introduction
	2 Investigation Based on Simulation
	3 Modeling Ids Hump for BT SOI
	4 Discussions
	References
IR-LED Using Electroluminescence in PbS Quantum Dot
	1 Introduction
	2 Experimental
	3 Results and Discussion
	4 Conclusions
	References
100X Increase in Industrial and Personal Productivity Augmenting the State-of-the-Art Technologies AI/ML, Edge Computing, and 5G Network
	1 Introduction
		1.1 Challenges
		1.2 Secure AI in Multi-Stakeholder Environments
		1.3 The AI@EDGE Connect–Compute Fabric for Beyond 5G Networks
		1.4 A. Distributed and Decentralized Connect–Compute Platform
	2 Conclusions
	References