DSP for Embedded and Real-Time Systems

0iii_Front-Matter
	DSP for Embedded and Real-Time Systems: Expert Guide
0iv_Copyright
	Copyright
0xv_Author-Biographies
	Author Biographies
0xxiii_DSP-in-Embedded-Systems-A-Roadmap
	DSP in Embedded Systems: A Roadmap
		Phase 1 – Product Specification
		Phase 2 – Algorithmic Modeling
		Phase 3 – Hardware/Software Partitioning
		Phase 4 – Iteration and Selection
		Phase 5 – Real-Time Software Design
			1. Part 1; Identify the stimuli for processing and required responses to the stimuli
			2. Identify timing constraints for each stimuli and response
			3. Aggregate stimulus and response processing into concurrent processes
			4. Design algorithms to process stimulus and response, meeting the given timing requirements
			5. Design a scheduling solution ensuring processes are scheduled in time to meet their deadlines
		Phase 6 – Hardware/Software Integration
01_Chapter-1-Introduction-to-Digital-Signal-Processing
	1 - Introduction to Digital Signal Processing
		What is digital signal processing?
		Advantages of DSP
		DSP systems
			Analog-to-digital conversion
			The Nyquist criteria
			Digital-to-analog conversion
		Applications for DSPs
			Low cost DSP applications
		Power efficient DSP applications
			High performance DSP applications
		Conclusion
015_Chapter-2-Overview-of-Real-time-and-Embedded-Systems
	2 - Overview of Real-time and Embedded Systems
		Real-time systems
			Soft and hard real-time systems
			Differences between real-time and time-shared systems
			DSP systems are hard real-time
				Hard real-time systems
			Real-time event characteristics
		Efficient execution and the execution environment
			Resource management
		Challenges in real-time system design
			Response time
			Recovering from failures
		Distributed and multi-processor architectures
			Initialization of the system
			Processor interfaces
			Load distribution
			Centralized resource allocation and management
		Embedded systems
			Embedded systems are reactive systems
		Summary
029_Chapter-3-Overview-of-Embedded-Systems-Development-Lifecycle-Using-DSP
	3 - Overview of Embedded Systems Development Lifecycle Using DSP
		Embedded systems
		The embedded system lifecycle using DSP
			Step 1 – Examine the overall needs of the system
				What is a DSP solution?
			Step 2 – Select the hardware components required for the system
			Hardware gates
			Software programmable
			General purpose processors
			Microcontrollers
		FPGA solutions
			Digital signal processors
		A general signal processing solution
		DSP acceleration decisions
			Step 3 – Understand DSP basics and architecture
		Models of DSP processing
			Input/output options
			Calculating DSP performance
			DSP software
		Code tuning and optimization
		Typical DSP development flow
		Putting it all together
063_Chapter-4-Programmable-DSP-Architectures
	4 - Programmable DSP Architectures
		Common features of programmable DSP architectures
			DSP core and ISA features
				Features of the programmable DSP space
				Issues surrounding use of SIMD operations
				Predicated execution
		Memory architecture
			Access sizes
			Alignment issues
		Data operations
075_Chapter-5-FPGA-in-Wireless-Communications-Applications
	6 - FPGA in Wireless Communications Applications
		Introduction
			Spatial multiplexing MIMO systems
			Flex-Sphere detector
				Tree Traversal for Flex-Sphere detection
			Modified real-valued decomposition (M-RVD) ordering
			FPGA design of the configurable detector for SDR handsets
				PED computations
				Configurable design
					Number of Antennas
					Modulation Order
			Modified real-valued decomposition (M-RVD)
				Timing analysis
			Xilinx FPGA implementation results for Mr=3
			Xilinx FPGA implementation results for Mr=3
			Simulation results
		Beamforming for WiMAX
			Beamforming in wideband systems
			Computational requirements and performance of a beamforming system
			Beamforming experiments using WARPLab
				WARPLab framework
			Experiment setup and results
		Conclusion
		References
0103_Chapter-6-The-DSP-Hardware-Software-Continuum
	6 - The DSP Hardware/Software Continuum
		Introduction
		FPGA in embedded design
			FPGA computational throughput and power
			Algorithm suitability
			Fixed point versus floating point
			Implementation challenges
		Application specific integrated circuits versus FPGA
			Advantages of ASICs over FPGAs
		Software programmable digital signal processing
		General purpose embedded cores
		Putting it all together
			Architecture
			Application driven design
		Bibliography
0113_Chapter-7-Overview-of-DSP-Algorithms
	7 - Overview of DSP Algorithms
		Applications of DSP
		Systems and signals
			DSP systems
			Aliasing
		The basic DSP system
			Filters
				FIR filters
				IIR filters
		Frequency analysis
			Convolution
			Correlation
			Designing an FIR filter
				Parks-McClellan algorithm
			Windowing
				Adding feedback using IIR filters
		Algorithm implementation – DSP architecture
			Number format
			Overflow and saturation
		Implementing an FIR filter
			Utilizing on-chip RAM
			Special MAC instruction
			Block filtering
			Separate program and data busses
			Zero overhead looping
			Circular buffers
		System issues
		Conclusion
0133_Chapter-8-High-level-Design-Tools-for-Complex-DSP-Applications
	8 - High-level Design Tools for Complex DSP Applications
		High-level synthesis design methodology
		High-level design tools
		Catapult C
			PICO
			System Generator
		Case studies
		LDPC decoder design example using PICO
		Matrix multiplication design example using Catapult C
		QR decomposition design example using System Generator
		Conclusion
		References
0157_Chapter-9-Optimizing-DSP-Software-Benchmarking-and-Profiling-DSP-Systems
	9 - Optimizing DSP Software – Benchmarking and Profiling DSP Systems
		Introduction
		Writing a test harness
			Test harness inputs, outputs, and correctness checking
		Isolating a DSP kernel
			Protecting against aggressive build tools
			Allowing flexibility for code placement
		Modeling of true system behaviors
			Cache effects
			Memory latency effects
		System effects
			RTOS overhead
		Execution in a multicore/multidevice environment
			Methods for measuring performance
				Time-based measurement
				Hardware timers
				Performance counter-based measurement
				Profiler-based measurement
		Measuring the measurement
			Excluding non-related events
			Interrupts
			Runtime library functions used in the benchmark
			Simulated measurement
			Hardware measurement
			Profiling results
			How to interpret results
				How to use them to optimize code
0169_Chapter-10-Optimizing-DSP-Software-High-level-Languages-and-Programming-Models
	10 - Optimizing DSP Software – High-level Languages and Programming Models
		Assembly language
			Advantages and disadvantages
		C Programming language with intrinsics and pragmas
			Outline placeholder
				Standard C integral types
			FIR in C
			Intrinsic functions
				Fractional types and saturation
				Floating point
				Custom types
			Pragmas
				Function pragmas
				Statement pragmas
				Variable pragmas
		Embedded C
		C++ for embedded systems
		Auto-vectorizing compiler technology
			Matlab, Labview and FFTW-like generator suites
			Matlab and native compiled code
			Native code to Matlab and silicon emulation
0181_Chapter-11-Optimizing-DSP-Software-Code-Optimization
	11- Optimizing DSP Software – Code Optimization
		Optimization process
		Using the development tools
			Compiler optimization
			Basic compiler configuration
				Target architecture
				Endianness
				Memory model
				Initial optimization level
			Enabling optimizations
			Additional optimization configurations
			Using the profiler
			Analyzing compiled code
		Background – understanding the DSP architecture
			Resources
		Basic C optimization techniques
			Choosing the right data types
		Use of intrinsics to leverage DSP features
			Functions
				Calling conventions
		Pointers and memory access
			Ensuring alignment
			Restrict and pointer aliasing
		Loops
			Communicating loop count information
		Hardware loops
		Additional tips and tricks
			Memory contention
			Use of unaligned accesses
			Cache accesses
			Inline small functions
			Use vendor DSP libraries
		General loop transformations
		Loop unrolling
			Background
			Implementation
		Multisamping
			Background
			Implementation procedure
			Implementation
		Partial summation
			Background
			Implementation procedure
			Implementation
		Software pipelining
			Background
			Implementation
		Example application of optimization techniques: cross correlation
			Setup
				Initial port
			Original implementation
				Performance analysis – Freescale StarCore SC3850 Core
			Step 1: Use intrinsics for fractional operations and specify loop counts
				Performance analysis – Freescale StarCore SC3850 Core
			Step 2: Specify data alignment and modify for multisampling algorithm
				Performance analysis – Freescale StarCore SC3850 Core
			Step 3: Assembly language optimization
				Performance analysis – Freescale StarCore SC3850 Core
0217_Chapter-12-DSP-Optimization-Memory-Optimization
	12 - DSP Optimization – Memory Optimization
		Introduction
		Code size optimizations
			Compiler flags and flag mining
			Target ISA for size and performance tradeoffs
			Tuning the ABI for code size
			Caveat emptor: compiler optimization orthogonal to code size!
		Memory layout optimization
			Overview of memory optimization
			Focusing optimization efforts
			Vectorization and the dynamic code-compute ratio
				Pointer aliasing in C
			Data structures, arrays of data structures, and adding it all up!
			Loop optimizations for memory performance
			Data alignment’s rippling effects
			Selecting data types for big payoffs
0241_Chapter-13-Software-Optimization-for-Power-Consumption
	13 - Software Optimization for Power Consumption
		Introduction
		Understanding power consumption
			Static versus dynamic power consumption
				Static power consumption
				Dynamic power consumption
					Maximum, average, worst case, and typical power
		Measuring power consumption
			Measuring power using an ammeter
			Measuring power using a Hall Sensor type IC
			Voltage regulator module power supply ICs
				slink8
					Static power measurement
					Dynamic power measurement
		Profiling your application’s power consumption
		Minimizing power consumption
			Hardware support
				Low power modes
				Freescale’s MSC815x low power modes
				Texas Instruments C6000 low power modes
		Clock and voltage control
			Considerations and usage examples of low power modes
				Low power example
					At application start up
					During application runtime
		Optimizing data flow
			Reducing power consumption for memory accesses
			DDR overview
			DDR data flow optimization for power
				Optimizing power by timing
				Optimizing with interleaving
				Optimizing memory software data organization
				Optimizing general DDR configuration
				Optimizing DDR burst accesses
				SRAM and cache data flow optimization for power
				SRAM (all memory) and code size
				SRAM power consumption and parallelization
				Data transitions and power consumption
				Cache utilization and SoC memory layout
				Explanation of Locality
				Explanation of Set-Associativity
				Memory layout for cache
				Write back versus write through caches
				Cache coherency functions
				Compiler cache optimizations
		Peripheral/communication utilization
			DMA of data versus CPU
				Coprocessors
				System bus configuration
				Peripheral speed grades and bus width
				Peripheral to core communication
				Interrupt processing
			Algorithmic optimization
				Compiler optimization levels
				Instruction packing
				Loop unrolling
				Software pipelining
			Eliminating recursion
				Reducing accuracy
				Low-power code sequences and data patterns
		Summary and closing remarks
		References
0291_Chapter-14-DSP-Operating-Systems
	14 - DSP Operating Systems
		Introduction
		DSP OS fundamentals
		Real-time constraints
			Processes, threads and interrupts
				Process
				Thread
				Task
				Interrupt
				Interrupt latency
				Software interrupt
		Multicore considerations
			Peripherals sharing
				Synchronization primitives
		Memory management
			Memory allocation
			Virtual memory and memory protection
				Different types of memory
		Networking
			Inter-processor communication
			Internetworking
		Scheduling
			Reference model
				Timing constraints
				Timing characteristics
				Precedence graph
			Preemptable vs. non-preemptable scheduling
			Blocking vs. non-blocking jobs
			Cooperative scheduling
			Types of scheduling
			Multicore considerations on scheduling
			Offline scheduling and its possible implementation
				Some possible enhancements
			Online scheduling (priority based scheduling)
			Static priority scheduling
				Rate monotonic scheduling
				Deadline monotonic schedule
			Dynamic priority scheduling
				Earliest deadline first
			Offline versus online scheduling
			Priority inversion
				Disabling scheduler
				Priority inheritance
				Priority ceiling
		Tools support for DSP OSes
		Conclusions
		References
0335_Chapter-15-Managing-the-DSP-Software-Development-Effort
	15 - Managing the DSP Software Development Effort
		Introduction
		Challenges in DSP application development
		The DSP design process
			Concept and specification phase
				A specification process for DSP systems
				Algorithm development and validation
			DSP algorithm standards and guidelines
			High level system design and performance engineering
				Performance engineering
			Software development
			System build, integration, and test
			Factory and field test
		Design challenges for DSP systems
		High level design tools for DSP
		DSP toolboxes
		Host development tools for DSP development
		A generic data flow example
			Debug – verifying code performance
		Code tuning and optimization
			Typical DSP development flow
			Getting started
		Putting it all together
0361_Chapter-16-Multicore-Software-Development-for-DSP
	16 - Multicore Software Development for DSP
		Introduction
		Multcore programming models
			Multiple-single-cores
				Advantages of multiple-single-cores
				Disadvantages of multiple-single-cores
				Characteristics of multiple-single-cores applications
			True-multiple-cores
				Advantages of true-multiple-cores
				Disadvantages of true-multiple-cores
		Porting guidelines
			Design considerations
			Motion JPEG case study
				JPEG encoding
					Input data
					Discrete cosine transfer
					Zig-zag reordering
					Quantization
					Run-length coding
					Huffman coding
				Design considerations
					Input
					Scheduling
					Inter-core communication
					Output
			Implementation details
				Scheduling
				Inter-core communication
				Input and output
		Conclusions
0493_Case-Study-2-DSP-for-Medical-Devices
	2 - DSP for Medical Devices
		Medical imaging introduction
		Ultrasound basics
		Ultrasound transducer
		Imaging modes
		Doppler effect basics
		High level system overview
			Overview of classic beamforming
			Design use case
		Echo processing
		Conclusions
		References
0523_Case-Study-3-Voice-Over-IP-DSP-Software-System
	3 - Voice Over IP DSP Software System
		Brief VoIP Domain Introduction
			Wired TDM telecom network
			Migration to IP based transport, market drivers, and technical changes
		DSP role in VoIP applications
			TDM-IP Media Gateway
			A DSP Framework for the VoIP Applications
		DSP centric architectural details of a Media Gateway
			High level architecture of a Media Gateway and the DSP VoIP application
				System Software Functionalities
		TDM to IP processing path in a Media Gateway
		DSP VoIP Framework differentiators
			Support for legacy equipment
				Phase distortions
				Delay Compensation Mechanism
		DSP VoIP framework differentiators
			DTMF detection
				Sections
					DTMF specifications; Q.23 and Q.24 recommendations
					DTMF specifications
					ITU-T Q.23 recommendation
					ITU-T Q.24 recommendation
					Q.24 compliant DTMF detection algorithm example
			The Goertzel filters
				The peak filters
				Notch filters
				Power estimation module
				LCU (Level Control Unit) modules
				TK loops
		References
0571_Case-Study-4-Software-Performance-Engineering-of-an-Embedded-System-DSP-Application
	3 - Software Performance Engineering of an Embedded System DSP Application
		Introduction and Project Description
			Initial Performance Estimates and Information Requirements
			Developing the Initial Estimate
			Tracking and Reporting the Metrics
			Reducing the Measurement Error
		Conclusions and Lessons Learned
		References
0587_Case-Study-5-Specifying-Behavior-of-Embedded-Systems
	5 - Specifying Behavior of Embedded Systems
		What makes a good requirement?
			Sequence Enumeration
				Assumptions
			It's really all just math!
0599_Case-Study-6-DSP-for-Software-Defined-Radio
	6 - DSP for Software Defined Radio
		Introduction
			Functional architecture of a base station
				General partition
				LTE eNodeB
				UMTS and HSPA NodeB
				Joint architecture
			Processor
			Software architecture
		Conclusion
0611_Index
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