Digitally Enhanced Mixed Signal Systems

Cover
Contents
Preface
1 Digitally enhanced mixed signal systems—the big picture
	1.1 Motivation
	1.2 Methodology
		1.2.1 A system-oriented perspective
		1.2.2 An extended view on data converters
		1.2.3 The design process
	1.3 Examples
		1.3.1 Enhancing power amplifiers
			1.3.1.1 Crest factor reduction
			1.3.1.2 Digital predistortion
			1.3.1.3 Burst-mode transmitter
		1.3.2 Enhancing data converters
		1.3.3 Enhancing clock generation
	1.4 Conclusion
	References
2 Nonlinear modeling
	2.1 Introduction
	2.2 Nonlinear models
		2.2.1 Parametric models
			2.2.1.1 Memoryless models
			2.2.1.2 Memory models
		2.2.2 Nonparametric models
			2.2.2.1 Neural network
	2.3 Suited models for each RF bloc
		2.3.1 Extension to complex models
		2.3.2 Models for power amplifiers
			2.3.2.1 Circuit-level PA models
			2.3.2.2 System-level PA models
			2.3.2.3 Memoryless models
			2.3.2.4 Memory models
		2.3.3 Models for low-noise amplifiers
		2.3.4 Models for baseband blocks
	2.4 Digital compensation of nonlinear distortions
		2.4.1 Direct learning architecture
			2.4.1.1 Identification
			2.4.1.2 Inversion
		2.4.2 Indirect learning architecture
			2.4.2.1 Introduction
			2.4.2.2 Nonlinear system inverse estimation
	2.5 Summary
	References
3 Digital predistortion
	3.1 Why do we need predistortion?
		3.1.1 Waveform features
			3.1.1.1 Complementary cumulative distribution function
			3.1.1.2 Peak-to-average power ratio
			3.1.1.3 Frequency bandwidth
			3.1.1.4 Stationarity
		3.1.2 System level considerations
			3.1.2.1 Linearity–efficiency trade-off
			3.1.2.2 System level trade-off
			3.1.2.3 Figures of merit
	3.2 Principles of predistortion
	3.3 Analog vs digital predistortion
	3.4 Mathematical aspects
		3.4.1 Baseband formulation
		3.4.2 pth-Order inverse of linear system
	3.5 Models for DPD structures
		3.5.1 Parametric models
			3.5.1.1 Block-oriented nonlinear model
			3.5.1.2 Pruning of Volterra series
			3.5.1.3 Modified or dynamic Volterra series
			3.5.1.4 Orthogonal Volterra series
			3.5.1.5 Models with segmentation
			3.5.1.6 Switched models
			3.5.1.7 Neural networks models
		3.5.2 Nonparametric models
	3.6 Identification
		3.6.1 Indirect learning architecture
		3.6.2 Direct learning architecture
		3.6.3 DPD with iterative learning control (ILC)
	3.7 Wideband and subband processing
	3.8 Multidimensional predistortion
		3.8.1 Linearization of noncontiguous carrier aggregation
		3.8.2 Multiple input multiple output
	3.9 Model sizing
		3.9.1 Model sizing by hill climbing heuristic
		3.9.2 Model sizing by integer genetic algorithm
		3.9.3 Model sizing using orthogonal matching pursuit (OMP) algorithm
	3.10 Joint mitigation of various impairments
		3.10.1 Cooperation with crest factor reduction (CFR)
		3.10.2 Processing of imperfections
			3.10.2.1 IQ imbalance and DC offset compensation
			3.10.2.2 Load mismatch or variation of power amplifier gain
	3.11 Overview of companion signal processing
		3.11.1 Synchronization
		3.11.2 Sampling frequency
		3.11.3 Monitoring
	3.12 Implementation
	3.13 Conclusion
	References
4 Digital post-distortion of radio receivers and analog-to-digital converters
	4.1 Motivations for post-distortion of radio receivers and ADCs
		4.1.1 Ideal vs. practical radio receiver
		4.1.2 Dynamic range issues of modern radio receivers
		4.1.3 Principle of post-distortion
		4.1.4 Figures of merit
	4.2 Review of distortions issues met in radio receivers
		4.2.1 Distortion issue of IF-digitising superheterodyne receivers
		4.2.2 Distortion issue of low-IF receivers
		4.2.3 Distortion issue of full-digital receivers
	4.3 Model-based post-distortion: modelling
		4.3.1 The passband Volterra model
		4.3.2 The baseband Volterra model
		4.3.3 Physical interpretation and dimensioning of Volterra model non-linearity order and memory depth
		4.3.4 Derivatives of Volterra model
		4.3.5 Modelling ADCs
		4.3.6 Modelling IF-digitising superheterodyne and full-digital receivers
		4.3.7 Modelling low-IF receivers
		4.3.8 On the usage of baseband Volterra model for reducing computational burden of passband Volterra model
		4.3.9 On sampling frequency required for non-linear system modelling
	4.4 Model-based post-distortion: identification and inversion
		4.4.1 Statements of the model identification problem
		4.4.2 Dealing with the need of both distorted and undistorted signal samples
		4.4.3 Solution of direct Wiener filter problem
		4.4.4 Inversion of a model determined by a direct identification scheme
		4.4.5 On the numerical instability issue
			4.4.5.1 About persistence of a system excitation
			4.4.5.2 Numerical analysis of the persistence of an excitation
			4.4.5.3 Physical interpretation of the persistence of an excitation
		4.4.6 Effects of numerical instability on the least square solution
		4.4.7 Effects of numerical instability on stochastic least mean square and recursive least square solutions
			4.4.7.1 Simple and normalised stochastic least mean square algorithms
			4.4.7.2 Recursive least square algorithm
	4.5 Study of an example of ADC and receiver model-based post-distortion solution
		4.5.1 Targeted system features
		4.5.2 Block diagram of the post-distortion solution
		4.5.3 Modelling features
		4.5.4 Identification features
		4.5.5 Inversion features
		4.5.6 Results of post-distortion operated on a simulated full-digital receiver
		4.5.7 Results of post-distortion operated on the targeted system
	4.6 Look-up-table-based post-distortion of ADCs
		4.6.1 LUT-based post-distortion strategies
		4.6.2 Determination of LUT values
		4.6.3 INL sequence modelling
	4.7 Conclusion
	References
5 Time or frequency interleaved analog-to-digital converters
	5.1 Introduction
	5.2 Principle of time-interleaved ADCs and impacts of mismatches
		5.2.1 TIADC principle
		5.2.2 The impact of channel mismatches
			5.2.2.1 Offset mismatch
			5.2.2.2 Gain mismatch
			5.2.2.3 Timing mismatch
			5.2.2.4 Bandwidth mismatch
	5.3 State of the art of interleaved channel mismatches compensation
		5.3.1 Analog compensation techniques
		5.3.2 Mixed signal compensation techniques
		5.3.3 Digital compensation
	5.4 Feedforward background calibration technique of clock skews
		5.4.1 Digital estimation
		5.4.2 Digital correction
		5.4.3 Calibration for input at any Nyquist band
	5.5 Feedback calibration technique of bandwidth mismatches
		5.5.1 Frequency–response mismatch model
		5.5.2 Theoretical channel mismatches estimation
		5.5.3 Channel mismatches compensation
			5.5.3.1 Periodic time-varying correction block
			5.5.3.2 Discrete-time-correlation-based estimation block
		5.5.4 Simulation results
			5.5.4.1 Two interleaved channels and a nine-tone input signal
			5.5.4.2 Four interleaved channels and a nine-tone input signal
			5.5.4.3 Hardware acquisition of single-tone input signals
	5.6 Extended frequency band decomposition Σ Δ A/D converter
		5.6.1 EFBD architecture
		5.6.2 Digital reconstruction system (DS)
		5.6.3 Adaptation algorithms
	5.7 Conclusion
	References
6 Digitally enhanced digital-to-analogue converters
	6.1 Overview
	6.2 Digital-to-analogue converters
		6.2.1 Converter implementation
		6.2.2 Converter errors
	6.3 DAC linearisation
		6.3.1 Calibration
		6.3.2 Dynamic element matching
	6.4 Harmonic-cancelling DAC with partial DEM
		6.4.1 Harmonic-cancelling sine wave generation
		6.4.2 Dynamic element matching in HC-DACs
		6.4.3 Experimental results
	6.5 Summary
	References
7 Clock generation
	7.1 Development of advanced PLLs
	7.2 ADPLL-based transmitter
	7.3 Ultra-low-voltage, ultra-low-power ADPLL for IoT applications
	7.4 Switched-capacitor DC–DC converter
	7.5 Low-voltage ADPLL architecture with PVT-tolerant TDC
	7.6 Switching current-source oscillator
	7.7 Calibration for PVT-insensitive time-to-digital converter (TDC)
	7.8 Design of high-efficiency switched-capacitor doubler/regulator for event-based load
	7.9 Implementation and experimental results
	7.10 Conclusion
	References
8 Fixed-point refinement of digital signal processing systems
	8.1 Introduction
	8.2 Fixed-point arithmetic
		8.2.1 Fixed-point representation
		8.2.2 Format propagation
			8.2.2.1 Addition–subtraction
			8.2.2.2 Multiplication
			8.2.2.3 Division
		8.2.3 Quantisation process and rounding modes
			8.2.3.1 Truncation
			8.2.3.2 Conventional rounding
			8.2.3.3 Convergent rounding
		8.2.4 Overflow modes
	8.3 Architecture support for fixed point
		8.3.1 Fine-grained word-length operators
		8.3.2 Mid and coarse-grained word-length operators
			8.3.2.1 Multi-precision operations
			8.3.2.2 Exploitation of sub-word parallelism with SIMD
	8.4 Fixed-point conversion process
	8.5 Integer-part word-length selection
		8.5.1 Dynamic range evaluation
			8.5.1.1 Interval-based methods
			8.5.1.2 Statistical methods
			8.5.1.3 Stochastic methods
		8.5.2 IWL determination and insertion of scaling operations
	8.6 Fractional-part word-length determination
		8.6.1 Word-length optimisation
			8.6.1.1 Optimisation algorithms
			8.6.1.2 Comparison of optimisation techniques
		8.6.2 Accuracy evaluation
			8.6.2.1 Simulation-based approaches
			8.6.2.2 Analytical approaches
	8.7 Conclusion
	References
9 Adaptive filtering
	9.1 Introduction
	9.2 Algorithm presentations
		9.2.1 Least mean square algorithm
			9.2.1.1 Principle and mathematical formulation
			9.2.1.2 Discussion
			9.2.1.3 Complexity assessment and step size tuning rules
		9.2.2 Affine projection algorithms
			9.2.2.1 Convergence rate of the APA
			9.2.2.2 Steady state
		9.2.3 Recursive least square
			9.2.3.1 Exponentially weighted least square criterion
			9.2.3.2 Recursive implementation
			9.2.3.3 RLS algorithm parameters
			9.2.3.4 Fast RLS algorithms
		9.2.4 Nonlinear algorithms
			9.2.4.1 Sign algorithms
			9.2.4.2 Stability and convergence rate of the SD-LMS, SE-LMS and SS-LMS
			9.2.4.3 Leaky LMS
			9.2.4.4 Least mean forth algorithm
			9.2.4.5 Proportionate NLMS
			9.2.4.6 Dual-sign algorithm
	9.3 Algorithm comparison
		9.3.1 Complexity comparison
		9.3.2 Implementation and cost
		9.3.3 Discussion
	9.4 Application
		9.4.1 Context and model
		9.4.2 Floating-point and fixed-point model
	9.5 Conclusion
	References
Index
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