Digitally-Assisted Analog and RF CMOS Circuit Design for Software-Defined Radio

8.2.1 Architecture......Page 3
 7.3 Delta-Sigma () ADC......Page 5
 4.3 UCLA SDR-RX......Page 7
Cover......Page 1
Digitally-Assisted Analog and RF CMOS CircuitDesign for Software-Defined Radio......Page 4
 Preface......Page 6
  8.2.3 Mixers as Power Generation Units......Page 9
Chapter 1: Introduction......Page 10
  8.2.4 Signal Combing at the Output Network......Page 11
  7.5.2 Noise Effect......Page 13
  8.3.1 Architecture Overview......Page 14
  8.3.2 Power Mixer Unit......Page 16
  2.3.1 Reconfigurable PLL......Page 17
  2.3.2 LC Voltage Controlled Oscillators......Page 18
 8.4 Measurement Results......Page 19
  2.3.3 Programmable Divider......Page 20
 2.5 Transmitter......Page 27
  2.5.2 The Mixer......Page 29
 2.2 SDR Architecture......Page 15
  2.4.1 Low-Noise Amplifiers......Page 21
  2.4.2 Passive Mixer and IIP2 Calibration......Page 22
 5.7 Experimental Results......Page 23
  5.7.4 Two-Stage Polyphase HR......Page 26
  2.5.1 The Transmit Baseband Section......Page 28
  2.5.3 The Pre-power Amplifier......Page 30
 2.6 Measurement Results......Page 31
  3.7.4 High-Rate IIR Filtering......Page 33
  3.7.5 Additional Spatial MA Filtering Zeros......Page 34
  3.7.6 Lower-Rate IIR Filtering......Page 36
 2.7 Conclusions......Page 38
  3.7.9 Signal Processing Example......Page 39
  3.7.10 MTDSM Feedback Path......Page 41
  3.1.1 Analog-Intensive RF Transceivers......Page 43
  3.1.2 Digitally-Intensive RF Transceivers......Page 45
 References......Page 46
  7.2.2 Sampling Frequency......Page 2
 Contents......Page 8
 2.1 Introduction......Page 12
  2.4.4 SAR ADC......Page 25
  2.4.3 Analog Baseband Chain......Page 24
 References......Page 35
 References......Page 40
 3.2 New Paradigm of RF Design in Nanometer-Scale CMOS......Page 47
 3.3 RF-SoC Landscape......Page 49
 3.4 Digital RF Processor (DRPTM)......Page 52
  3.4.1 Patents on Digital RF......Page 53
 3.5 All-Digital Phase-Locked Loop (ADPLL)......Page 55
  3.5.1 ADPLL Phase-Domain Operation......Page 57
  3.5.2 ADPLL Implementation......Page 58
   3.5.2.1 Digitally-Controlled Oscillator......Page 60
   3.5.2.2 Time-to-Digital Converter (TDC)......Page 61
 3.6 All-Digital Transmitter......Page 63
  3.6.1 Digital Power Amplifier......Page 64
   3.6.2.1 Towards Multirate ADPLL Operation......Page 65
   3.6.2.2 Frequency Modulator Within an All-Digital Polar Transmitter......Page 68
   3.6.2.3 Phase Detector in the Multirate ADPLL......Page 70
  3.7.1 Receiver Architecture......Page 71
  3.7.2 Direct Sampling Mixer......Page 72
  3.7.3 Temporal Moving-Average......Page 73
  3.7.4 High-Rate IIR Filtering......Page 75
  3.7.5 Additional Spatial MA Filtering Zeros......Page 76
  3.7.6 Lower-Rate IIR Filtering......Page 78
  3.7.7 Cascaded MTDSM Filtering......Page 80
  3.7.8 Near-Frequency Interferer Attenuation......Page 81
  3.7.10 MTDSM Feedback Path......Page 83
 3.8 RF Built-In Self-Test (RF-BIST)......Page 85
 3.9 Conclusion......Page 87
 References......Page 88
 4.1 Introduction......Page 92
  4.2.1 Mitola's Architecture......Page 93
  4.2.2 Direct Conversion with Digital Front-End Decimation Architecture......Page 94
  4.2.3 Sampler with Bulit-In Anti-Aliasing......Page 95
   4.2.3.2 RF-WIS Role in Wireless Receivers......Page 96
   4.2.3.3 Baseband-WIS Role in Wireless Receivers......Page 97
 4.3 UCLA SDR-RX......Page 98
  4.3.1 Pre-ADC Analog Signal Conditioner in Narrowband Receivers......Page 99
  4.3.2 UCLA Low-Power SDR-RX: Architecture and System Design......Page 100
   4.3.2.1 Low Power ADCs at Baseband......Page 102
   4.3.2.3 Programmable Baseband Filter with RWIS Core......Page 103
   4.3.2.4 Examples of Synthesis of RWIS-DTDec......Page 104
  4.3.3 UCLA SDR-RX: Circuit Realization......Page 106
   4.3.3.1 RWIS-DTDec Filter Circuit Realization......Page 107
   4.3.3.2 Gain Programmability of RWIS-DTDec Filter......Page 110
   4.3.3.3 Wideband Radio Front-End Circuits......Page 111
  4.3.4 SDR-RX Prototype......Page 116
 4.4 Summary......Page 117
 References......Page 118
 5.1 Introduction......Page 120
  5.1.2 Nonlinearity......Page 121
  5.1.3 Harmonic Mixing......Page 123
  5.1.4 Contribution of this Chapter......Page 124
  5.2.1 Concept......Page 125
  5.2.2 Realization......Page 127
 5.3 Two-Stage Polyphase Harmonic Rejection......Page 128
  5.3.1 Block Diagram......Page 129
  5.3.2 Working Principle......Page 130
 5.4 Digitally-Enhanced Harmonic Rejection......Page 132
  5.4.1 Generating the Interference Estimate......Page 134
  5.4.2 The Adaptive Interference Canceller......Page 135
  5.5.1 Linear Low-Noise Transconductance Amplifier (LNTA)......Page 137
  5.5.2 Accurate Multiphase Clock......Page 138
  5.5.3 High-Swing TIA and Baseband R-Net......Page 139
 5.6 Implementation of the Digital Back-End......Page 140
 5.7 Experimental Results......Page 142
  5.7.2 Out-of-Band IIP2/IIP3......Page 143
  5.7.3 One dB Compression Point and Blocker Filtering......Page 144
  5.7.4 Two-Stage Polyphase HR......Page 145
  5.7.5 Digitally-Enhanced HR......Page 146
  5.7.6 Comparing the Alternatives......Page 147
  5.7.7 Performance Summary and Benchmark......Page 148
 References......Page 154
 6.1 Introduction......Page 158
  6.2.1 Architecture......Page 159
  6.2.2 Duty-Cycle-Controlled Discrete-Time Transconductor......Page 161
  6.2.3 Reconfigurable DT Filter......Page 165
  6.2.4 Anti-aliasing Filter......Page 166
  6.2.5 Variable Duty-Cycle Pulse Generator......Page 170
 6.3 Measurement Results......Page 171
 6.4 Conclusion......Page 175
 7.1 Introduction......Page 177
  7.2.1 Signal Bandwidth......Page 178
  7.2.3 Resolution......Page 180
 7.3 Delta-Sigma () ADC......Page 181
 7.4 Basic Block Diagram of Delta-Sigma ADCs......Page 184
 7.5 Delta-Sigma ADCs for Multi-Standard Applications......Page 186
  7.5.1  Resolution, Order and Sampling Frequency......Page 187
  7.5.2 Noise Effect......Page 189
  7.5.3 Signal Bandwidth and Power Consumption......Page 192
 7.6 Digital-to-Analog Converters (DAC)......Page 193
 References......Page 195
 8.1 Introduction......Page 196
  8.2.1 Architecture......Page 198
  8.2.2 Segmented Power Generation......Page 199
  8.2.3 Mixers as Power Generation Units......Page 204
  8.2.4 Signal Combing at the Output Network......Page 206
  8.2.5 Digital LO Amplification Versus Conventional Analog Driver Amplifiers......Page 207
  8.3.1 Architecture Overview......Page 209
  8.3.2 Power Mixer Unit......Page 211
  8.3.4 Digital LO Distributor......Page 212
  8.3.5 Analog BB Distributor and Controller......Page 214
 8.5 Conclusion......Page 219
 References......Page 220
Index......Page 221