Digital microfluidic biochips: synthesis, testing, and reconfiguration techniques

 Content: PART I    SYNTHESIS TECHNIQUES   Introduction    Technology Issues    Digital Microfluidic Biochips    Microfluidic Biochip Design Challenges    Book Outline   Architectural-Level Synthesis    Background    High-Level Synthesis Methodology    Simulation Experiments   Module Placement    Background    Module Placement Problem    Fault Tolerance for Digital Microfluidic Biochips    Experimental Evaluation   Unified Synthesis Methodology    Problem Formulation    PRSA-Based Algorithm    Enhancement for Defect Tolerance    Experimental Evaluation   Droplet Routing    Background    Problem Formulation    Routing Method    Experimental Evaluation   PART II    TESTING TECHNIQUES   Test Methodology    Background    Classification of Faults    Unified Detection Mechanism    Parametric Fault Testing    Simulation Experimental Setup   Test Planning    Problem Definition    Analysis of Computational Complexity    Integer Linear Programming Model for OPP    Heuristic Algorithms    Simulation Results  Concurrent Testing    Concurrent Testing Methodology    Optimal Scheduling for Concurrent Testing    Concurrent Testing Example   Defect-Oriented Testing and Diagnosis    Fault Modeling    Defect-Oriented Experiment    Testing and Diagnosis    Real-Life Application   PART III    RECONFIGURATION TECHNIQUES  Reconfiguration Schemes    Proposed Reconfiguration Schemes    Example Evaluation   Defect Tolerance Based on Space Redundancy    Background    Microfluidic Array with Hexagonal Electrodes    Defect-Tolerant Designs    Estimation of Yield Enhancement    Evaluation Example   Defect Tolerance Based on Graceful Degradation    Tile-Based Architecture    Clustered Defect Model   Graceful Degradation with Reconfiguration    Simulation Results   Conclusions and Future Work    Contributions of the Book    Future Work   Bibliography    Index