Digital Logic: With an Introduction to Verilog and FPGA-Based Design

Cover
Title Page
Copyright
Contents
Preface
Chapter 1: Introduction to Digital Systems
	1.1 Explanation of Terms
	1.2 Design Levels
	1.3 Combinational vs. Sequential Systems
	1.4 Digital Circuits
		1.4.1 Diodes
		1.4.2 Transistors
		1.4.3 MOS Transistors
	1.5 Integrated Circuits (ICs
	1.6 CAD (Computer-Aided Design
	1.7 Evolution of Digital Logic, Microprocessors, and Microcontrollers
	1.8 A Typical Application of a Digital System such as a Microcontroller
Chapter 2: Number Systems, Arithmetic/Logic Operations, and Codes
	2.1 Number Systems
		2.1.1 General Number Representation
		2.1.2 Converting Numbers from One Base to Another
	2.2 Unsigned and Signed Binary Numbers
	2.3 Codes
		2.3.1 Binary-Coded-Decimal Code (8421 Code
		2.3.2 Alphanumeric Codes
		2.3.3 Excess-3 Code
		2.3.4 Gray Code
		2.3.5 Unicode
	2.4 Fixed-Point and Floating-Point Representations
	2.5 Arithmetic Operations
		2.5.1 Binary Arithmetic
		2.5.2 BCD Arithmetic
		2.5.3 Multiword Binary Addition and Subtraction
		2.5.4 Binary Multiplication and Division by Shift Operations
	2.6 Error Correction and Detection
	QUESTIONS AND PROBLEMS
Chapter 3: Digital Logic Gates, Boolean Algebra, and Simplification
	3.1 Basic Logic Operations
		3.1.1 NOT Operation
		3.1.2 OR operation
		3.1.3 AND operation
	3.2 Other Logic Operations
		3.2.1 NOR operation
		3.2.2 NAND operation
		3.2.3 Exclusive-OR operation (XOR
		3.2.4 Exclusive-NOR Operation (XNOR
	3.3 Positive and Negative Logic
	3.4 Boolean Algebra
		3.4.1 Boolean Identities
		3.4.2 Simplification Using Boolean Identities
		3.4.3 Consensus Theorem
		3.4.4 Getting Rid of Glitches or Hazards in Combinational Circuits
		3.4.5 Complement of a Boolean Function
	3.5 XOR / XNOR Implementations
	QUESTIONS AND PROBLEMS
Chapter 4: Minterms, Maxterms, and Karnaugh Map
	4.1 Standard Representations
	4.2 Karnaugh Maps
		4.2.1 Two-Variable K-map
		4.2.2 Three-Variable K-map
		4.2.3 Four-Variable K-map
		4.2.4 Prime Implicants
		4.2.5 Expressing a Boolean function in Product-of-sums (POS) form using a K-map
		4.2.6 Don’t Care Conditions
		4.2.7 Five-Variable K-map
	4.3 Quine–McCluskey Method
	4.4 Implementation of Digital Circuits with NAND, and NOR Gates
		4.4.1 NAND Gate Implementation
		4.4.2 NOR Gate Implementation
	QUESTIONS AND PROBLEMS
Chapter 5: Analysis and Design of Combinational Circuits Using Gates
	5.1 Basic Concepts
	5.2 Analysis of a Combinational Logic Circuit
	5.3 Design of Combinational Circuits Using Logic Gates
	5.4 Multiple-Output Combinational Circuits
	QUESTIONS AND PROBLEMS
Chapter 6: Design of Typical Combinational Logic Components
	6.1 Design of Typical Combinational Logic Components
	6.2 Comparators
	6.3 Decoders
	6.4 Encoders
	6.5 Multiplexers
	6.6 Demultiplexers
	6.7 Binary Adder/Subtractor and BCD Adder
	QUESTIONS AND PROBLEMS
Chapter 7: Combinational Shifter, Fast Adders, Array Multipliers, ALU, & PLDs
	7.1 Combinational Shifter
	7.2 Central Processing Unit (CPU)
	7.3 Arithmetic Logic Unit (ALU)
	7.4 Read-Only Memories (ROMs)
	7.5 Programmable Logic Devices (PLDs)
	7.6 Commercially Available Field Programmable Devices (FPDs)
	QUESTIONS AND PROBLEMS
Chapter 8: Combinational Logic Using Verilog
	8.1 Hardware Description Languages (HDLs)
	8.2 Basics of Verilog
		8.2.1 Verilog keywords
		8.2.2 Representing numbers in Verilog
		8.2.3 A typical Verilog Segment
	8.3 Structural Modeling
	8.4 Dataflow Modeling
	8.5 Behavioral modeling
		8.5.1 if-else block
		8.5.2 Modeling logical conditions in a circuit
		8.5.3 Case-endcase construct
		8.5.4 Conditional Operator
	8.6 Simulation
	QUESTIONS AND PROBLEMS
Chapter 9: Latches and Flip-Flops
	9.1 Latches and Flip-Flops
		9.1.1 SR Latch
		9.1.2 Gated SR Latch
		9.1.3 Gated D Latch
		9.1.4 Edge-Triggered D Flip-Flop
		9.1.5 JK Flip-Flop
		9.1.6 T Flip-Flop
	9.2 Timing parameters for edge-triggered flip-flops
	9.3 Preset and Clear Inputs
	9.4 Summary of Flip-Flops
	QUESTIONS AND PROBLEMS
Chapter 10: Analysis and Design of Sequential Circuits
	10.1 Introduction
	10.2 Analysis of Synchronous Sequential Circuits
	10.3 Types of Synchronous Sequential Circuits
	10.4 Minimization of States
	10.5 Design of Synchronous Sequential Circuits
	10.6 Serial Adder
	10.7 Sequence Generator/Detector
	10.8 Random-Access Memory (RAM
	10.9 Algorithmic State Machines (ASM) Chart
	10.10 Asynchronous Sequential Circuits
	QUESTIONS AND PROBLEMS
Chapter 11: Counters and Registers
	11.1 Design of Counters
	11.2 Design of Registers
		11.2.1 Shift Register
		11.2.2 “Shift register” Counters
		11.2.3 General-Purpose Register (GPR)
	QUESTIONS AND PROBLEMS
Chapter 12: Sequential Logic Design Using Verilog
	12.1 Basics
	12.2 Examples Illustrating Non-blocking and Blocking Assignments
	12.3 RTL (Register Transfer Level) modeling
	QUESTIONS AND PROBLEMS
Chapter 13: Implementation of Digital Design Using FPGA
	13.1 Basics of FPGA
		13.1.1 LUTs (Look-Up Tables)
		13.1.2 Programmable Switch Matrix
		13.1.3 Configurable Logic Blocks (CLBs)
		13.1.4 FPGA Architecture
		13.1.5 FPGA Programming
	13.2 A Typical FPGA Chip
		13.2.1 Configuration Pins
		13.2.2 User I/O Pins
		13.2.3 Power/Ground Pins
	13.3 A Typical FPGA Board
	13.4 FPGA-based Design and Implementation
		13.4.1 Design
		13.4.2 Synthesis
		13.4.3 Implementation, Programming, and Verification
	13.5 FPGA Examples
	QUESTIONS AND PROBLEMS
Appendix A: Answers to Selected Problems
Appendix B: Glossary
Appendix C: Step-By-Step Tutorial For Downloading And Installing Xilinx Vivado IDE
Appendix D: Step-By-Step Tutorial For Creating & Simulating A Verilog Design Using Xilinx Vivado IDE
	I COMBINATIONAL CIRCUIT
	II SEQUENTIAL CIRCUIT
Appendix E: Step-By-Step Procedure For Implementing FPGA-Based Design Using Vivado IDE & Nexys A7 FPGA Board
	I COMBINATIONAL CIRCUIT
	II FPGA IMPLEMENTATION OF SEQUENTIAL CIRCUIT
Bibliography
Index
EULA