Digital Front-End in Wireless Communications and Broadcasting: Circuits and Signal Processing

Cover......Page 1
Title......Page 5
Copyright......Page 6
Contents......Page 7
Contributors......Page 14
Preface......Page 19
Part I Introduction to digital front-end......Page 27
1 Introduction to wireless communications and digital broadcasting......Page 29
1.1 Evolution of mobile cellular networks......Page 30
1.1.2 Second-generation cellular systems......Page 32
1.1.4 Future broadband wireless communications......Page 33
1.2.2 Digital broadcast system......Page 35
ATSC Terrestrial......Page 36
DVB-T......Page 37
ISDB-T......Page 38
1.2.3 Mobile TV......Page 39
1.3.1MIMO......Page 41
Interference reduction......Page 42
Spatial multiplexing gain......Page 43
Diversity gain......Page 44
1.3.2 OFDM......Page 45
1.3.3 Cognitive radio......Page 48
1.4 Conclusions......Page 49
References......Page 50
2.1 Introduction......Page 54
2.2 Digital processing, transmission, and reception......Page 55
2.3 The WCDMA/OFDMA physical layer protocols......Page 58
2.4 General principles of MIMO systems......Page 65
2.5 Space-time and space-frequency transmission over MIMO networks......Page 70
References......Page 74
3.1 Introduction......Page 76
3.2.1 New and emerging wireless communication standards......Page 82
3.2.2 Overview of UMTS......Page 85
3.2.3.1 Long Term Evolution (LTE)......Page 89
3.2.3.2 Mobile WiMAX......Page 98
3.3 Other emerging standards beyond 3G......Page 102
3.4 DFE introductory design considerations......Page 105
3.4.1 Transceiver issues associated with software defined radio......Page 109
3.4.2 Power amplifier issues......Page 110
3.4.3 Technology aspects......Page 114
3.4.4 Digital processing devices: DSP and FPGA......Page 115
List of abbreviations (Chapter 3)......Page 117
References......Page 121
4.1 Introduction......Page 124
4.2 Broadcast mobile multimedia services......Page 128
4.3 Common technologies for digital mobile broadcast services......Page 129
4.4.1 DVB-RCT......Page 131
4.4.2 DVB-H......Page 132
4.4.3 DVB-SH......Page 133
4.4.5 MediaFLO......Page 134
4.4.6 MBMS......Page 135
4.5.2 ADC and DAC converters......Page 137
4.5.3 Some characteristics of the power amplifiers......Page 138
List of abbreviations (Chapter 4)......Page 142
References......Page 144
5.1 Introduction......Page 146
5.2 Receiver architectures......Page 148
5.3 Analog-to-digital converters......Page 152
5.4 Preselect filters and LNA interface for multiband receivers......Page 154
5.5 Power amplifier architectures in multimode-multiband transmitters......Page 156
5.5.1 PA structures for multimode-multiband handsets......Page 157
5.5.2 Multi-amplifier arrangements in power transmitters......Page 158
5.6 Conclusions......Page 161
List of abbreviations (Chapter 5)......Page 162
References......Page 163
Part II DPD and CFR......Page 167
6.2 Power amplifier nonlinearity......Page 169
6.3.1 Digital predistortion challenges......Page 176
6.3.2 Adaptive digital predistortion......Page 180
6.3.3 Learning-based digital predistortion......Page 184
6.4 Digital predistortion basics......Page 186
6.5.1 Model order selection......Page 203
6.6.1 Other work and key researchers......Page 213
6.6.3 Conclusion......Page 214
References......Page 215
7.1 Introduction......Page 218
7.2 Principles of predistortion linearization......Page 219
7.3 Power amplifier behavioral models for digital predistortion......Page 222
Saleh model......Page 224
7.3.2 Power amplifier behavioral models with memory effects......Page 225
Artificial neural networks: time delay neural networks......Page 226
Volterra series based models......Page 228
Memory polynomial: nonlinear moving average behavioral models......Page 229
Augmented nonlinear moving average......Page 230
Hammerstein model......Page 231
Wiener model......Page 233
Wiener–Hammerstein cascade: three-box modeling......Page 234
Nonlinear auto-regressive moving average models......Page 235
7.4 Discussion......Page 236
References......Page 237
8.1 Introduction......Page 240
8.2.1 LUT schemes......Page 241
8.2.2 LUT size and word length......Page 243
8.2.3 LUT spacing......Page 244
8.3 FPGA implementation of an LUT-based DPD......Page 245
Indirect learning: postdistortion and translation method......Page 246
Predictive predistortion method......Page 250
8.3.2 Implementation of the adaptive DPD function in an FPGA......Page 252
External adaptation......Page 253
External adaptation results......Page 259
Near real-time adaptation......Page 261
Near real-time adaptation results......Page 264
8.4 Discussion......Page 266
References......Page 267
9 Digital predistortion and its combination with crest factor reduction......Page 270
9.1 Principles of operation......Page 271
9.2.1 Memoryless system......Page 272
Look-up table......Page 273
Polynomial Functions......Page 274
Volterra series......Page 275
Generalized memory polynomial......Page 276
Dynamic deviation reduction (DDR)-based Volterra model......Page 277
Vector threshold decomposition......Page 278
Model inverse structure......Page 281
Model reference structure......Page 282
9.4.1 The receiver chain......Page 283
9.4.2 The transmit chain......Page 284
9.5.1 Excitation signal selection......Page 285
9.5.2 Data acquisition......Page 286
9.5.4 Data normalization......Page 287
9.5.5 Model extraction algorithms......Page 288
9.6 Implementation considerations......Page 290
9.7 Combination with crest factor reduction......Page 296
9.7.1 Clipping and filtering......Page 297
9.7.2 Peak windowing......Page 298
9.7.4 Selected mapping......Page 299
9.7.5 Tone reservation......Page 300
9.7.6 Tone injection......Page 301
9.8 Conclusions and future outlook......Page 302
References......Page 303
10.1 Introduction......Page 306
10.2.1 Quantifying PA nonlinearity......Page 307
10.2.2 System modeling of PA nonlinearity......Page 310
10.3.1 Memoryless nonlinear models......Page 312
10.3.2 Memory nonlinear models......Page 313
10.3.3 Indirectly learning architecture for system identification......Page 317
10.3.4 Estimation of predistorter coefficients......Page 319
10.3.5 DPD performance and experimental results......Page 322
10.4.1 Adaptive DPD architecture......Page 324
10.4.2 Fixed-point challenges......Page 325
10.4.3 Implementation considerations......Page 330
References......Page 331
11.1 Introduction......Page 335
11.2 Multi-carrier communication systems......Page 337
11.2.2 PAPR/CF reduction techniques......Page 339
Tone Injection......Page 340
Tone Reservation......Page 341
Companding techniques......Page 342
Selected mapping......Page 343
Interleaving......Page 344
11.3 CF reduction using clipping plus filtering......Page 345
Model for bandpass clipping-and-filtering simulation......Page 347
11.3.2 Simulation results and comparison......Page 348
References......Page 352
Part III DUC, DDC, ADC, DAC, and NCO......Page 357
12 Digital down-conversion and up-conversion: theory and implementation......Page 359
12.1 Introduction......Page 360
12.1.1.1 Bandpass sampling......Page 361
12.1.1.2 Oversampling......Page 363
12.1.2.1 Direct digital synthesizer......Page 364
12.2 Multi-rate, multi-stage, and filter-banks in DDC and DUC......Page 365
12.2.1 I/Q demodulation in DDC (I/Q mod. in DUC) and NCO......Page 366
12.2.2.1 Multi-rate and multi-stage filtering......Page 368
1.2.2.2 Filter bank implementation......Page 370
12.2.3 Sample rate conversion in DUC......Page 371
12.3 Mixing and combining for multi-channels and multi-carriers......Page 374
12.3.1 Mixing and combining for multi-channels......Page 375
12.3.2 Multimode radio DUC......Page 376
12.4 Introduction......Page 378
12.4.2.1 DC offset cancellation design......Page 382
12.4.2.2 DC offset cancellation implementation......Page 384
12.4.3 Direct digital synthesizer......Page 386
12.4.3.1 Direct digital synthesizer design......Page 387
12.4.3.2 Direct digital synthesizer implementation......Page 388
12.4.4.2 Decimation filtering......Page 390
12.4.4.3 Multi-rate filter implementation......Page 392
14.5 Hardware implementation for digital up-conversion......Page 396
12.5.1 Introduction......Page 398
12.5.2.2  Multi-rate interpolation filtering implementation......Page 399
12.5.3 DUC performance......Page 402
12.6 Summary......Page 403
References......Page 404
13 A/D and D/A data conversion for wireless communications transceivers......Page 406
13.1 A/D conversion in RF receiver......Page 407
13.1.1 ADC dynamic range......Page 408
13.1.2 Equivalent number of bits......Page 409
13.1.3 Linearity of ADC......Page 411
13.2 ADC for heterodyne and low-IF receiver......Page 412
13.3.1 Multiplying technique......Page 415
13.3.3 Subsampling technique......Page 416
13.4 Implementation of ADCs in communications receivers......Page 418
13.4.1 Multi-standard ∑Δ ADCs......Page 420
13.4.2 Pipeline ADC......Page 422
13.5.1 EVM and ENOB......Page 423
13.5.2 Linearity of DAC......Page 425
13.5.3 Digital images in DAC......Page 427
13.7 Implementation of DACs in communications transmitters......Page 428
13.7.1 Baseband and IF DACs......Page 432
13.7.2 RF DACs......Page 433
13.8 Summary......Page 435
References......Page 436
14.1 Sigma-delta basics......Page 439
14.1.1 Lowpass modulator......Page 441
14.1.2 Real bandpass modulator......Page 443
14.1.3 Quadrature bandpass modulator......Page 445
14.1.3.1 First-order quadrature modulator......Page 447
14.1.3.2 Higher-order quadrature modulator......Page 452
14.2.2 Modulator order......Page 453
14.2.3 Single-stage vs. multi-stage......Page 454
14.2.3.1 Leslie–Singh Modulator......Page 455
14.2.3.2 Multi-stage noise shaping (MASH)......Page 456
14.3.1 Quadrature multi-stage modulator......Page 457
14.3.2 Multiband quadrature modulator......Page 458
14.3.3 Multiband quadrature multi-stage modulator......Page 459
14.4.1 Nonlinearities......Page 460
14.4.3 I/Q imbalance in quadrature ΣΔ modulators......Page 461
14.5 Examples on complex multiband transfer function design......Page 465
14.5.1 Single-stage multiband with I/Q imbalance......Page 466
14.5.2 Multi-stage multiband with I/Q imbalance......Page 469
14.6 Conclusion......Page 471
References......Page 472
15 Digital suppression of A/D interface nonlinearities......Page 476
15.1.1 Basics......Page 478
15.1.2 Clipping phenomenon......Page 481
15.2 Look-up table......Page 482
15.3 Dithering......Page 484
15.4 Model inversion......Page 485
15.5.1 Basic principle......Page 486
15.5.2 Implementation example......Page 488
15.5.3 Enhanced adaptive interference cancellation......Page 490
15.6 Clipping compensation using interpolation......Page 491
15.7.1 Clipping compensation......Page 493
15.7.2 INL mitigation......Page 495
15.8 Conclusions......Page 496
References......Page 497
Part IV Digital calibration, imbalance compensation, and error corrections......Page 499
16.1 Introduction......Page 501
16.2 I/Q modulation and direct-conversion radio architecture......Page 502
16.3.1 Frequency-independent imbalance modeling......Page 503
16.3.2 Frequency-dependent I/Q imbalance modeling......Page 505
16.3.3 Alternative imbalance models based on parallel I/Q signals and illustrations......Page 507
16.4.1 Principle of TX calibration using pre-distortion......Page 508
16.4.2 Principle of RX calibration using post-distortion......Page 509
OFDM link models......Page 510
MIMO-OFDM link models......Page 511
RX-based estimation techniques......Page 513
TX-internal imbalance estimation......Page 514
16.4.5 Blind or non-data-aided imbalance estimation methods......Page 516
Moment-based estimator for frequency-dependent RX I/Q imbalance compensation utilizing the circularity condition......Page 517
Frequency-dependent RX I/Q imbalance compensation based on iterative re-circularization......Page 519
16.5.1 Direct-conversion transmitter I/Q calibration with widely linear least squares model fitting based method......Page 520
16.5.2 Blind circularization-based methods in a dual-carrier direct-conversion receiver......Page 521
16.6 Conclusions......Page 523
References......Page 524
17.1 Introduction......Page 528
17.2 Effects of IQM impairments on PA intermodulation products and predistorter estimation......Page 530
17.2.2 Effect of I/Q mismatch......Page 532
17.2.3 Effect of IQM impairments on adaptive predistorter estimation......Page 534
17.3.1 Volterra-based structure......Page 536
17.3.2 Parallel Hammerstein-based structure......Page 538
17.4.1 Indirect learning......Page 540
17.4.2 Block least squares estimation......Page 541
17.4.3 Recursive least squares solution......Page 543
17.4.4 Practical aspects......Page 544
17.5 Simulation and measurement examples......Page 545
17.5.1 Simulation example 1 – OFDM direct-conversion Tx......Page 546
17.5.2 Simulation example 2 – SC-FDMA low-IF Tx......Page 548
17.5.3 Simulation example 3 – comparison between block and recursive algorithms......Page 549
17.5.4 Simulation example 4 – effect of fractional delay......Page 550
17.5.5 Measurement results......Page 551
17.6 Conclusions......Page 553
References......Page 554
18.1 Introduction......Page 557
18.2.2 OFDM signal generation......Page 558
18.2.3 OFDM signal reception......Page 561
18.2.4 Multipath channel......Page 563
18.2.5 Channel estimation and equalizer......Page 564
18.2.6 OFDM communication and broadcasting systems......Page 565
18.2.7.1 WLAN system overview......Page 567
18.2.7.2 WLAN system architecture......Page 568
18.2.8.1 OFDMA transceiver system overview......Page 569
18.2.8.2 SC-FDMA transceiver overview......Page 571
18.2.8.3 OFDMA transceiver architecture......Page 572
18.3.1 Introduction to multiple antenna receivers......Page 573
18.3.2.1 OFDM-directed array antenna system......Page 575
18.3.2.2 OFDM selective Maximum Ration Combining (MRC)......Page 576
18.3.3.1 MRC for uniformly distributed branch noise......Page 577
18.3.3.2 MRC for independently distributed branch noise......Page 579
18.3.4 Hybrid diversity......Page 580
18.4.1 Time domain RF error detection and compensation......Page 582
18.4.2 Time domain FFT window position detection and RF error detection......Page 583
18.4.3 Time domain RF error, sampling error, and symbol timing detection and compensation......Page 584
18.4.4 Frequency domain RF error and sampling error detection......Page 585
18.4.5 Delay profile detection and frequency domain FFT position detection......Page 587
18.4.6 FFT window shift detection by constellation rotation and compensation......Page 588
18.5.1 Four antenna adaptive array combiner LSI [7]......Page 589
18.5.2 A 2/4/8 Antennas Configurable Diversity OFDM Receiver LSI [16]......Page 590
18.5.3 Joint hardware-software implementation of adaptive array antenna OFDM receiver by FPGA [9]......Page 591
18.5.4 Hybrid pre-FFT adaptive array antenna and post-FFT space diversity combining for Mobile ISDB-T Receiver by FPGA [19]......Page 595
References......Page 597
19.1 Introduction......Page 599
19.2.1 Front-end stack up for multiband or multi-antenna systems......Page 600
19.2.2 Multiplexing techniques......Page 603
19.3.1 Double orthogonal frequency front-end architecture dedicated to bi-band reception......Page 606
19.3.2 UMTS and WiFi simultaneous reception study case......Page 607
19.3.3 Digital method dedicated to the mitigation of the orthogonal defaults impact on the double IQ receiver performance......Page 608
19.4.1 RF impairments mitigation via antenna processing......Page 611
SIMO mitigation phase noise......Page 612
Frequency offset......Page 613
IQ mismatch......Page 614
19.4.2.1 Structure of the code multiplexing architecture......Page 615
19.5 Front-ends combining multiband and multi-antenna capabilities......Page 617
Study case......Page 618
Multi-* performance.......Page 619
19.5.2 Combining code multiplexing and double IQ structure......Page 621
19.6 Conclusions......Page 624
References......Page 625
Part V Circuits and system integration in digital front-end......Page 627
20.1 Introduction......Page 629
20.2 Mixed signal transceiver architectures......Page 630
20.2.1 Receiver design for TDD narrowband GSM/GPRS/EDGE......Page 631
20.2.2 Receiver design for FDD LTE/HSPA/WCDMA......Page 632
20.2.3 Transmitter design for TDD narrowband GSM/GPRS/EDGE......Page 634
20.2.4 Transmitter design for FDD LTE/HSPA/WCDMA......Page 635
20.3.1.1 Direct down-conversion......Page 636
20.3.1.2 Near ZIF down-conversion......Page 637
20.3.2 LTE/HSPA/WCDMA receiver Analog–Digital systems......Page 638
20.3.4.1 Direct conversion......Page 642
20.3.4.2 Digital IF system......Page 643
20.4 Conclusions and discussions......Page 644
References......Page 645
21.1 Introduction......Page 646
21.2 Major Functions of the DFE......Page 647
ARX specifications......Page 648
Close-in filtering requirements......Page 651
21.4 Design of DFE to support WCDMA and GGE......Page 652
Principle of polynomial resampling......Page 653
The first rate change filter......Page 656
Prefilter and resampler......Page 658
Decimation by 2 at resampler output......Page 665
GGE data path......Page 668
WCDMA data path......Page 670
21.5 Considerations to support LTE......Page 672
References......Page 674
22.2 Programming environment and tools for SDR......Page 676
DSP Centric Platforms......Page 677
22.2.2 Waveform description language......Page 678
Wilink Waveform Description Language......Page 679
VANU RDL (Radio Description Language)......Page 680
E2R FDL (Functional Description Language)......Page 681
SPEX Language......Page 682
UPC radio software framework......Page 683
22.3 An existing radio virtual machine implementation......Page 684
Computation model......Page 685
Execution model......Page 686
22.3.2 Physical Layer Description Language......Page 687
Data flow access methods......Page 688
22.3.3 RVM implementation issues......Page 690
22.3.4 Performance results for a CFO IEEE802.11a......Page 692
References......Page 694
23.1 Background......Page 697
23.1.1 Active resistor–capacitor filters......Page 698
23.1.2 Switched-capacitor filters......Page 699
23.1.3 Transconductor–capacitor filters......Page 700
23.2.1 Sampling theory......Page 701
23.2.2 Z-transform......Page 702
23.2.4 Finite impulse response filters......Page 703
23.2.5 Sensitivity comparison......Page 704
23.2.6 Decimation......Page 706
23.2.7 Charge domain sampling......Page 707
23.3.1 Advantages and disadvantages of zero IF receivers......Page 710
23.3.3 Example zero IF receiver......Page 712
23.4.3 Example low IF receiver system......Page 714
23.5 Case study of a super-heterodyne AM/FM radio receiver......Page 718
23.5.1 RF tracking filter......Page 720
23.5.2 Intermediate frequency filter......Page 724
23.5.3 Channel-select filter and analog-to-digital converter......Page 726
23.5.4 AM low-pass filter......Page 727
23.6 Summary and conclusions......Page 729
References......Page 730
24.1 Introduction......Page 733
24.2.1 Multi-port interferometer for quadrature down-conversion......Page 735
24.2.2 Multi-port interferometer for direct modulation......Page 739
24.2.3 Multi-port interferometer for antenna array......Page 741
24.3 Multi-port V-band practical implementation, modeling, and analysis......Page 744
24.4 Proposed transceiver architectures......Page 748
24.5 Advanced system simulations......Page 753
References......Page 757
25.1 Introduction to flexible cognitive wireless link......Page 759
25.2 A high-level optimization for SDR: multimode relaying......Page 762
25.2.1 Power consumption model......Page 763
25.2.1.2 Radio energy model......Page 764
25.2.2.1 Scenarios explained......Page 765
25.2.2.2 PHY layer only evaluation: UMTS-WiFi scenario......Page 767
25.2.2.3 PHY+MAC evaluation: WiFi+ZigBee scenario......Page 768
25.2.3 Multimode energy consumption summary......Page 772
25.3.1.1 Wireless microphone sensing......Page 773
25.3.1.2 Cyclostationarity-based OFDM sensing......Page 775
25.3.2.1 Adaptation of the cyclostationarity detector......Page 776
25.3.2.2 Decision threshold computation......Page 777
25.3.2.3 Filter’s characteristics......Page 778
25.3.2.4 Hardware architecture......Page 779
25.4 Conclusion......Page 781
References......Page 782
Index......Page 784