Digital electronics : principles and applications

Cover
Contents
Chapter 1: NUMBER SYSTEM
	1.1 Introduction
	1.2 Analog Systems
	1.3 Digital Systems
	1.4 Limitations of Digital Systems
	1.5 Digital Number Systems
	1.6 Binary Arithmetics
	1.7 Signed Magnitude
	1.8 One’s Complement
	1.9 Two’s Complement
	1.10 Subtraction by using Two’s Complement
	1.11 Overfl ow
	1.12 Binary Coded Decimal (BCD) Number System
	1.13 Packed BCD
	1.14 Gray Code (Refl ected Code)
	1.15 Gray Code to Binary Conversion
	1.16 Binary to Gray Code Conversion
	1.17 Excess-3 (XS3) Code
	1.18 Decimal to Excess-3 (XS3) Conversions
	1.19 Weighted BCD Codes
	1.20 ASCII Code
	1.21 EBCDIC
	1.22 Parity Bit
	1.23 Error Correcting Code: Hamming Code
	Summary
	Multiple Choice Questions
	Review Questions
Chapter 2: BOOLEAN ALGEBRA AND LOGIC GATES
	2.1 Introduction
	2.2 Boolean Algebra
	2.3 Boolean Laws
	2.4 De Morgan’s Theorem
	2.5 Logic Gates
	2.6 Universal Gate
	2.7 Simplifi cation of Logic Circuits
	2.8 Consensus Theorem
	2.9 Positive Logic and Negative Logic
	Summary
	Multiple Choice Questions
	Review Questions
Chapter 3: DIGITAL LOGIC FAMILY
	3.1 Introduction
	3.2 Classifi cation of Digital Logic Family
	3.3 Characteristics of Digital Logic Family
	3.4 BJT Characteristics
	3.5 Direct Coupled Transistor Logic (DCTL)
	3.6 Resistor Transistor Logic (RTL)
	3.7 Diode Transistor Logic (DTL)
	3.8 Transistor-Transistor Logic (TTL)
	3.9 Emitter Coupled Logic (ECL)
	3.10 Schottky TTL
	3.11 High Threshold Logic (HTL)
	3.12 Integrated Injection Logic (IIL)
	3.13 TTL Logic Gates
	3.14 Characteristics of TTL
	3.15 Metal Oxide Semiconductor FETs (MOSFET) Characteristics
	3.16 MOS Characteristics
	3.17 CMOS Gates
	3.18 CMOS Characteristics
	3.19 Interfacing TTL and CMOS Logic Family
	3.20 Advantages and Disadvantages of CMOS Over TTL
	Summary
	Multiple Choice Questions
	Review Questions
Chapter 4: COMBINATIONAL LOGIC
	4.1 Introduction
	4.2 Elements of Combinational Logic
	4.3 Boolean Equation
	4.4 Canonical Sum of Product (SOP)/Minterm Representation
	4.5 Canonical Product of Sum (POS)/Maxterm Representation
	4.6 Minterm vs. Maxterm
	4.7 Conversion between Canonical SOP and Canonical POS Forms
	4.8 Development of Truth Table from Logic Expression
	4.9 Logic Simplifi cation using Boolean Algebra
	4.10 Karnaugh Maps
	4.11 Construction of Karnaugh Maps from Logic Expression
	4.12 Logic Simplifi cation using Karnaugh Maps
	4.13 Product of Sums Simplifi cation using Karnaugh Maps
	4.14 Don’t Cares
	4.15 Minimisation of Simultaneous Functions
	4.16 Variable Mapping
	4.17 Tabular Method of Minimisation
	Summary
	Multiple Choice Questions
	Review Questions
Chapter 5: COMBINATIONAL LOGIC DESIGN
	5.1 Introduction
	5.2 Combinational Logic Design
	5.3 Decoders
	5.4 Encoders
	5.5 Priority Encoders
	5.6 Multiplexers
	5.7 Demultiplexer
	5.8 Code Conversion using Logic Gates and MSI ICs
	5.9 Hazards
	5.10 Fault Detection of Combinational Logic Circuit
	Summary
	Multiple Choice Questions
	Review Questions
Chapter 6: ARITHMETIC LOGIC CIRCUITS
	6.1 Introduction
	6.2 Binary Addition
	6.3 Binary Subtraction
	6.4 Carry Look-Ahead Addition
	6.5 Serial Adder
	6.6 Parallel Addition
	6.7 Binary Multiplier
	6.8 Binary Division
	6.9 Arithmetic Logic Units (ALU)
	6.10 Digital Comparators
	Summary
	Multiple Choice Questions
	Review Questions
Chapter 7: FLIP-FLOPS
	7.1 Introduction
	7.2 Inverter with Feedback
	7.3 Two Inverters form a Memory Cell
	7.4 Memory Cell using NAND and NOR Gates
	7.5 Latch
	7.6 S-R Latch using NOR Gates
	7.7 S-R Latch using NAND Gate
	7.8 S-R Latch with Enable
	7.9 The D Latch
	7.10 D Latch with Enable
	7.11 Flip-Flops
	7.12 Edge-triggered S-R Flip Flop
	7.13 Cascading S-R Flip-Flops
	7.14 S-R Flip-Flop with Asynchronous Inputs
	7.15 Edge-Triggered D Flip-Flops
	7.16 D Flip-Flop with Asynchronous Inputs
	7.17 The J-K Flip-Flop
	7.18 T Flip-Flop
	7.19 Conversion from One Type of Flip-Flop to Another Type
	7.20 Operating Characteristics of Flip-Flops
	7.21 Applications of Flip-Flops
	7.22 Flip-Flop ICs
	Summary
	Multiple Choice Questions
	Review Questions
Chapter 8: SEQUENTIAL CIRCUITS 3
	8.1 Introduction
	8.2 Register
	8.3 Shift Register
	8.4 Classifi cation of Shift Register
	8.5 Unidirectional Shift Registers
	8.6 Bi-directional Shift Registers
	8.7 Serial In-Parallel Out (SIPO) Shift Registers
	8.8 Serial In-Serial Out Shift Registers
	8.9 Parallel In-Parallel Out Shift Registers
	8.10 Parallel In-Serial Out Shift Registers
	8.11 Buffer Register
	8.12 Universal Shift Register
	8.13 Universal Shift Register using MUX
	8.14 Applications of Shift Registers
	8.15 Counter
	8.16 Classifi cation of Counter
	8.17 Asynchronous (Ripple) Counters
	8.18 Asynchronous Decade Counters
	8.19 Simultaneous Up-down Counter
	8.20 Asynchronous Up-down Counters
	8.21 Propagation Delay in Asynchronous Counter
	8.22 Asynchronous Counter ICs
	8.23 Synchronous Counters
	8.24 Synchronous Down Counter
	8.25 Synchronous Up-down Counters
	8.26 Synchronous Decade Counters
	8.27 Propagation Delay in Synchronous Counter
	8.28 Synchronous Counter ICs
	8.29 MOD n Counter
	8.30 Synchronous Counter Design Steps
	8.31 Cascade Counters
	8.32 Programmable or Presettable Counters
	8.33 Self Starting and Self Correcting Counters
	8.34 Counter Applications
	Summary
	Multiple Choice Questions
	Review Questions
Chapter 9: SEQUENTIAL CIRCUITS DESIGN
	9.1 Introduction
	9.2 Sequential Circuit Model
	9.3 Classifi cation of Sequential Circuits
	9.4 State Table
	9.5 State Diagram
	9.6 State Equation
	9.7 Design Procedure of Synchronous Sequential Circuits
	9.8 State Reduction of Synchronous Sequential Circuits
	9.9 Asynchronous Sequential Circuits
	9.10 Design Procedure of Asynchronous Sequential Circuits
	9.11 Algorithmic State Machines (ASM)
	Summary
	Multiple Choice Questions
	Review Questions
Chapter 10: MULTIVIBRATORS
	10.1 Introduction
	10.2 Classifi cation of Multivibrators
	10.3 Clock Oscillator using BJTs
	10.4 Monostable Multivibrator using BJTs
	10.5 Bistable Multivibrator using BJTs
	10.6 Astable Multrivibrator using NOT Gates
	10.7 Monostable Multrivibrator using NAND Gates
	10.8 Multivibrator using OP AMPs
	10.9 555 Timer
	10.10 Applications of 555 Timer
	10.11 556 Timer
	10.12 74121 Monostable Multivibrator
	10.13 74122 Retriggerable Monostable Multivibrator
	10.14 Retriggerable Monostable Multivibrator IC 74123
	Summary
	Multiple Choice Questions
	Review Questions
Chapter 11: ANALOG DIGITAL CONVERSION
	11.1 Introduction
	11.2 Sample and Hold Circuit
	11.3 Quantisation
	11.4 Binary Digit Weight
	11.5 Operational Amplifi ers
	11.6 Digital to Analog Converters (DAC)
	11.7 Extended Capacity of DAC
	11.8 Current Mode DAC
	11.9 Switched Capacitor DAC
	11.10 D/A Converter Specifi cation
	11.11 DAC ICs
	11.12 ADC Converter
	11.13 Medium Speed Analog to Digital Converters
	11.14 High Speed Analog to Digital Converters
	11.15 Specifi cation of ADC
	11.16 ADC ICs
	11.17 Bipolar DAC and ADC
	11.18 Applications of DAC and ADC
	Summary
	Multiple Choice Questions
	Review Questions
Chapter 12: SEMICONDUCTOR MEMORIES
	12.1 Introduction
	12.2 Classifi cation of Memory
	12.3 Memory Organisation
	12.4 Memory Operation
	12.5 Semiconductor Read-Only Memories
	12.6 Random-Access Memory (RAM)
	12.7 Sequential Memory
	12.8 Charge-Coupled Device (CCD)
	12.9 Magnetic Disks Memory
	12.10 Content-Addressable Memory (CAM)
	12.11 Advance Memory
	Summary
	Multiple Choice Questions
	Review Questions
Chapter 13: PROGRAMMABLE LOGIC DEVICES
	13.1 Introduction
	13.2 Programmable Read Only Memory (PROM) Devices
	13.3 Programmable Logic
	13.4 Programmable Logic Array (PLA)
	13.5 Programmable Array Logic (PAL)
	13.6 Comparison between PROM, PAL, and PLA
	13.7 Simple Programmable Logic Devices (SPLDs)
	13.8 Complex Programmable Logic Device (CPLDs)
	13.9 Field Programmable Gate Array (FPGA)
	Summary
	Multiple Choice Questions
	Review Questions
Chapter 14: COMPUTER AIDED DIGITAL SYSTEM DESIGN
	14.1 Introduction
	14.2 Computer Aided Digital System Design
	14.3 Computer Aided Design (CAD) Tools
	14.4 Hardware Description Language (HDL)
	14.5 Very High Speed Integrated Circuit Hardware Description Languages (VHDL)
	14.6 Verilog HDL
	Summary
	Multiple Choice Questions
	Review Questions
Chapter 15: LABORATORY EXPERIMENTS
	15.1 Introduction
	15.2 Development of Instruction Manual for Laboratory Experiments
	15.3 Experiment on Basic Logic Circuits using Diodes and Transistors
	15.4 Experiment on Basic Logic Circuits using Logic Gates
	15.5 Experiment on Combinational Logic Circuits using Logic Gates
	15.6 Experiment on Flip-Flops
	15.7 Experiment on Register
	15.8 Experiment on Seven Segment Display and Decoder Driver
	15.9 Experiment on Counters
	15.10 Experiment on Cascade Counters
	15.11 Experiment on Self Starting and Self Correcting Counters
	15.12 Experiment on Sequence Generator
	15.13 Experiment on Up-down Counter
	15.14 Experiment on Multivibrators
	15.15 Experiments on DAC
	15.16 Experiment on ADC
	15.17 Experiment on VHDL Simulation of Digital System
	Summary
	Review Questions
Appendix A: IEEE Standard Symbols
Appendix B: Pin Diagram of Logic Gates
Appendix C: Glossary
Appendix D: Answers of Multiple Choice Questions
Index