Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog

Contents
HDL CONTENT
CHAPTER OBJECTIVES
1.1 DIGITAL SYSTEMS
Practice Exercise 1.1
Practice Exercise 1.2
Practice Exercise 1.4
Practice Exercise 1.7
Practice Exercise 1.14 �C Using 2��s complements, find the following sums:
Practice Exercise 1.18
Register Transfer
Logic Gates
PROBLEMS
REFERENCES
WEB SEARCH TOPICS
CHAPTER OBJECTIVES
2.1 INTRODUCTION
2.2 BASIC DEFINITIONS
Two-Valued Boolean Algebra
Practice Exercise 2.2
Practice Exercise 2.6
Practice Exercise 2.12
2.7 OTHER LOGIC OPERATIONS
Practice Exercise 2.14
Computer-Aided Design of VLSI Circuits
PROBLEMS
REFERENCES
WEB SEARCH TOPICS
CHAPTER OBJECTIVES
3.1 INTRODUCTION
Practice Exercise 3.4
Five-Variable K-Map
Practice Exercise 3.8
Practice Exercise 3.9
Practice Exercise 3.11
Tabular Summary and Example
Parity Generation and Checking
VHDL Packages, Libraries, and Logic Systems
VHDL��Truth Tables
PROBLEMS
REFERENCES
WEB SEARCH TOPICS
CHAPTER OBJECTIVES
4.1 INTRODUCTION
4.2 COMBINATIONAL CIRCUITS
Practice Exercise 4.1
Code Conversion Example
Overflow
BCD Adder
4.7 BINARY MULTIPLIER
Practice Exercise 4.7
Combinational Logic Implementation
Priority Encoder
Three-State Gates
VHDL
VHDL (case Statement)
4.14 WRITING A SIMPLE TESTBENCH
4.15 LOGIC SIMULATION
PROBLEMS
REFERENCES
WEB SEARCH TOPICS
CHAPTER OBJECTIVES
5.1 INTRODUCTION
Practice Exercise 5.1
Practice Exercise 5.3
Practice Exercise 5.5
Practice Exercise 5.14
Practice Exercise 5.25��VHDL
State Assignment
Synthesis Using T Flip-Flops
PROBLEMS
REFERENCES
WEB SEARCH TOPICS
CHAPTER OBJECTIVES
Register with Parallel Load
Universal Shift Register
BCD Ripple Counter
Practice Exercise 6.3
Johnson Counter
Practice Exercise 6.3 �C VHDL
PROBLEMS
REFERENCES
WEB SEARCH TOPICS
CHAPTER OBJECTIVES
7.1 INTRODUCTION
Types of Memories
Address Multiplexing
Single-Error Correction, Double-Error Detection
Combinational PLDs
7.6 PROGRAMMABLE LOGIC ARRAY
7.7 PROGRAMMABLE ARRAY LOGIC
Xilinx Virtex FPGAs
PROBLEMS
REFERENCES
WEB SEARCH TOPICS
Chapter Objectives
8.1 INTRODUCTION
8.2 REGISTER TRANSFER LEVEL (RTL) NOTATION
Flowchart for Design
ASMD Chart��The Rosetta Stone of Systematic Design
Control Logic
VHDL?
ASMD Chart
One-Hot Design (One Flip-Flop per State)
VHDL?
Testing the Ones Counter
8.11 RACE-FREE DESIGN (SOFTWARE RACE CONDITIONS)
8.12 LATCH-FREE DESIGN (WHY WASTE SILICON?)
(case?.?.?.?inside)
PROBLEMS
REFERENCES
WEB SEARCH TOPICS
9.1 INTRODUCTION TO EXPERIMENTS
Other Counts
NAND Circuit
Complement
Decoder Implementation
Seven-Segment Display
Design Specifications
Magnitude Comparator
IC Flip-Flops
Design of Counter
Binary Counter with Parallel Load
Bidirectional Shift Register with Parallel Load
Serial Adder�CSubtractor
Memory Expansion
Lamp Ping-PongTM
Clock-Pulse Generator
Circuit Operation
Checking the Multiplier
HDL Supplement to Experiment 17 (Section 9.18)
10.1 RECTANGULAR-SHAPE SYMBOLS
10.2 QUALIFYING SYMBOLS
10.3 DEPENDENCY NOTATION
10.4 SYMBOLS FOR COMBINATIONAL ELEMENTS
10.5 SYMBOLS FOR FLIP-FLOPS
10.6 SYMBOLS FOR REGISTERS
10.7 SYMBOLS FOR COUNTERS
10.8 SYMBOL FOR RAM
PROBLEMS
REFERENCES
WEB SEARCH TOPICS
Appendix Semiconductors and CMOS Integrated Circuits
CMOS Characteristics
A.2 CMOS TRANSMISSION GATE CIRCUITS
Transmission Gate
WEB SEARCH TOPICS
Answers to Selected Problems
Answers to Selected Problems
Answers to Selected Problems
Answers to Selected Problems
Answers to Selected Problems
Answers to Selected Problems
Answers to Selected Problems
Answers to Selected Problems
Answers to Selected Problems
Index
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