Digital Design Techniques and Exercises: A Practice Book for Digital Logic Design

Preface
Acknowledgements
Contents
About the Author
1 Basics of Digital Design
	1.1 Digital Logic and the Evolution
	1.2 The Important Considerations
		1.2.1 Area of the Design
		1.2.2 Speed of the Design
		1.2.3 Power
	1.3 Logic Gates
	1.4 De Morgan’s Theorems
		1.4.1 NAND is Equal to Bubbled OR
		1.4.2 NOR is Equal to Bubbled AND
	1.5 Multiplexer as Universal Logic
	1.6 Optimization Goals and Applications in VLSI Context
	1.7 Exercises
		1.7.1 Exercise 1: Use of the Logical Expressions to Get the Logic Equivalent
		1.7.2 Exercise 2: Cascade Logic and How to Get Logic Expression?
		1.7.3 Exercise 3: Complement Logic
		1.7.4 Exercise 4: Logic Expression for the Cascade Logic
		1.7.5 Exercise 5: Output Expression for the Cascade Logic
		1.7.6 Exercise 6: Propagation Delay for the Cascade Logic
		1.7.7 Exercise 7: Logic Gate Output Expression
		1.7.8 Exercise 8: Propagation Delay for the Cascade Logic
		1.7.9 Exercise 9: The Equivalent Logic Expression 
		1.7.10 Exercise 10: The Equivalent Logic Gate
	1.8 Important Takeaways
2 Design Using Universal Logic
	2.1 What Is Universal Logic?
	2.2 Universal Gates
		2.2.1 NAND
		2.2.2 NOR
		2.2.3 Other Application-Specific Universal Gates
	2.3 Multiplexers
		2.3.1 Design Using 2:1 Mux
		2.3.2 4:1 MUX Using 2:1 Mux
		2.3.3 Design Using Multiplexers
	2.4 Exercises
		2.4.1 Exercise 1: Design Using Universal Gates
		2.4.2 Exercise 2: Design Using the MUX
		2.4.3 Exercise 3: Design Using MUX
		2.4.4 Exercise 4: Design Using Custom Gates
		2.4.5 Exercise 5: Optimization Exercise
		2.4.6 Exercise 7: Design Using the MUX
		2.4.7 Exercise 8: Design Using MUX
		2.4.8 Exercise 9: Design Using Custom Gates
	2.5 Applications and Use in VLSI Context
	2.6 Important Takeaways
3 Combinational Design Resources
	3.1 Code Converters
		3.1.1 Three-Bit Binary-to-Gray Code Converter
		3.1.2 3-Bit Gray-to-Binary Code Converter
	3.2 Arithmetic Resources
		3.2.1 Half-Adder
		3.2.2 Half-Subtractor
		3.2.3 Full-Adder
	3.3 Use of Arithmetic Resources in the Design
	3.4 Design Using Arithmetic Resources and Control Elements
	3.5 Optimization Goals
	3.6 Processor Logic and Need of Arithmetic Resources
	3.7 Exercises
		3.7.1 Exercise 1: Cascade Versus Parallel Logic
		3.7.2 Exercise 2: Delay of the Design
		3.7.3 Exercise 3: Speed
		3.7.4 Exercise 4: Design to perform the Addition and Subtraction
		3.7.5 Exercise 4: Design with the Goal to Use Resource Sharing
	3.8 Important Takeaways
4 Case Study: ALU Design
	4.1 Design Specifications and Their Role
	4.2 What Is ALU?
	4.3 Arithmetic Unit Design
		4.3.1 Resources Required
		4.3.2 How to Start Design of ALU?
		4.3.3 How to Design the Logic
		4.3.4 Exercise 1: Optimization of the Arithmetic Unit
		4.3.5 Logic Unit Design
		4.3.6 Resources Required
		4.3.7 How to Design the Logic Unit to have Better Area?
	4.4 ALU Design
		4.4.1 Resource Requirement and How to Design Efficient ALU?
		4.4.2 ALU Design to have Better Area
		4.4.3 Exercise 2: Optimization of ALU
	4.5 Few Important Design Guidelines
	4.6 Important Takeaways
5 Practical Scenarios and the Design Techniques
	5.1 Parallel Logic
		5.1.1 Decoder 2 to 4
	5.2 Encoder
	5.3 Encoder with Invalid Output Detection Logic
	5.4 Exercises
		5.4.1 Exercise 1: Design of Decoder Having Active-Low Output
		5.4.2 Exercise 2: Design the Function Using Decoder
		5.4.3 Exercise 3: Design Using Decoders
		5.4.4 Exercise 4: Design Using Decoder and NAND Gates
		5.4.5 Exercise 5: Design Using Decoders
		5.4.6 Exercise 6: Priority Encoder Design
	5.5 Important Takeaways
6 Basics of the Sequential Design
	6.1 What Is Sequential Logic Design?
	6.2 Sequential Design Elements
	6.3 Level Versus Edge-Triggered Logic
	6.4 Latches and Their Use in the Design
		6.4.1 Positive-Level-Sensitive D Latch
		6.4.2 Negative-Level-Sensitive D Latch
	6.5 Edge-Sensitive Elements and Their Role
		6.5.1 Positive Edge-Sensitive D Flip-Flop
		6.5.2 Negative Edge-Sensitive D Flip-Flop
	6.6 Applications
		6.6.1 Applications of the Latches
		6.6.2 Applications of the Flip-Flop
	6.7 Exercises
		6.7.1 Exercise 1: Design Positive-Level-Sensitive Latch Using Multiplexers
		6.7.2 Exercise 2: Design Negative-Level-Sensitive Latch Using Multiplexers
		6.7.3 Exercise 3: What Is the Functionality of the Following Design?
		6.7.4 Exercise 4: Design the Positive Edge-Sensitive Flip-Flop Using Latches
		6.7.5 Exercise 5: Design the Negative Edge-Sensitive Flip-Flop Using Latches
		6.7.6 Exercise 6: What Is the Operating Frequency of the Following Circuit?
		6.7.7 Exercise 7: The Asynchronous Clear
		6.7.8 Exercise 8: The Synchronous Clear
	6.8 Important Takeaways
7 Sequential Design Techniques
	7.1 Synchronous Design
	7.2 Asynchronous Design
	7.3 Why to Use Synchronous Design?
		7.3.1 Which Elements We Should Use During Design?
	7.4 D Flip-Flop and Use in the Design
	7.5 Design for the given specifications
	7.6 Design of the Synchronous Counters
	7.7 Exercise 1: Design of the Synchronous Down-Counters
	7.8 Exercise 2: Design of the Synchronous Gray Counter
	7.9 Few Important Guidelines
	7.10 Important Takeaways
8 Important Design Scenarios
	8.1 MOD-3 Counter
	8.2 The Design of MOD-3 Counter with 50% Duty Cycle
	8.3 Applications and Use of Counters
		8.3.1 Ring Counter
		8.3.2 Johnson Counter
	8.4 Exercises
		8.4.1 Exercise 1: The Counter Output
		8.4.2 Exercise 2: Find the Output Sequence
		8.4.3 Exercise 3: Operating Frequency of Design
		8.4.4 Exercise 4: Output on 1024th Clock Cycle
		8.4.5 Exercise 5: Output on the 4th Clock Cycle
		8.4.6 Exercise 6: Output at 10th Clock Pulse
		8.4.7 Exercise 7: Design the Serial Input Serial Output Shift Register
	8.5 Important Takeaways
9 FSM Design Techniques
	9.1 What Is FSM?
		9.1.1 Moore FSM
		9.1.2 Mealy FSM
		9.1.3 Moore Versus Mealy FSM
	9.2 State Encoding Methods
	9.3 Moore FSM Design
	9.4 Mealy FSM Design
	9.5 Applications and Design Strategies
	9.6 Exercises
		9.6.1 Exercise 1: Moore Machine State Diagram
		9.6.2 Exercise 2: Mealy Machine
		9.6.3 Exercise 3: One-Hot Encoding
		9.6.4 Exercise 4: FSM Area and Power Optimization
	9.7 Important Takeaways
10 Advanced Design Techniques-1
	10.1 Various Paths in the Design
	10.2 Data and Control Paths
	10.3 Mealy Sequence Detector Design
	10.4 Data and Control Path Design Techniques
	10.5 Flip-Flop Timing Parameters
	10.6 Example on Performance Improvement of the Design
	10.7 Exercises
		10.7.1 Exercise 1: Maximum Operating Frequency
		10.7.2 Exercise 2: Timing Paths
		10.7.3 Exercise 3: Maximum Operating Frequency
		10.7.4 Exercise 4: Positive Clock Skew and Maximum Operating Frequency for the Design
		10.7.5 Exercise 5: Negative Clock Skew and Maximum Operating Frequency for the Design
	10.8 Important Takeaways
11 Advanced Design Techniques-2
	11.1 Multiple Clock Domain Designs
	11.2 Metastability
	11.3 Control Path Synchronizer
	11.4 Data Path Synchronizer
	11.5 Multiple Power Domain Designs
	11.6 Architecture-Level Designs
	11.7 How We Can Improve the Design Performance
	11.8 The Digital Systems and Design
	11.9 Exercises
		11.9.1 Exercise 1: FIFO Depth Calculation
		11.9.2 Exercise 2: FIFO Depth Calculation
		11.9.3 Exercise 3: FIFO Depth Calculation
		11.9.4 Exercise 4: FIFO Depth Calculation
		11.9.5 Exercise 5: FIFO Depth Calculation
	11.10 Important Takeaways
12 System Design and Considerations
	12.1 System Design
	12.2 What We Need to Think About?
	12.3 Important Considerations
	12.4 Let Us Understand the Microprocessor Capabilities
	12.5 Control Signal Generation Logic
	12.6 IO Devices and Communication with the Processor
	12.7 Memory Devices and Communication with the Processor
	12.8 Design Scenarios and Optimization
	12.9 Concluding Comments
Index