Device Modelling for Analog and RF CMOS Circuit Design

Device Modeling for Analog and 
RF CMOS Circuit Design......Page 4
Copyright......Page 5
Contents......Page 6
Preface......Page 12
1.1 INTRODUCTION......Page 16
1.2 THE MOS CAPACITOR......Page 17
1.2.1 Interface Charge......Page 18
1.2.2 Threshold Voltage......Page 22
1.2.3 MOS Capacitance......Page 23
1.2.4 MOS Charge Control Model......Page 27
1.3 BASIC MOSFET OPERATION......Page 28
1.4 BASIC MOSFET MODELING......Page 30
1.4.1 Simple Charge Control Model......Page 31
1.4.2 The Meyer Model......Page 33
1.4.3 Velocity Saturation Model......Page 34
1.4.4 Capacitance Models......Page 36
1.4.5 Comparison of Basic MOSFET Models......Page 40
1.4.6 Basic Small- signal Model......Page 41
1.5 ADVANCED MOSFET MODELING......Page 42
1.5.1 Modeling Approach......Page 44
1.5.2 Nonideal Effects......Page 46
1.5.3 Uni . ed MOSFET C ¨C V Model......Page 52
REFERENCES......Page 59
2.1 INTRODUCTION......Page 62
2.2 TYPICAL PLANAR DIGITAL CMOS PROCESS FLOW......Page 63
2.3 RF CMOS TECHNOLOGY REFERENCES......Page 75
3.1 INTRODUCTION......Page 84
3.2 EQUIVALENT CIRCUIT REPRESENTATION OF MOS TRANSISTORS......Page 86
3.3 High-frequency Behavior of MOS Transistors and AC Small-signal
 Modeling......Page 93
3.3.1 Requirements for MOSFET Modeling for RF Applications......Page 94
3.3.2 Modeling of the Intrinsic Components......Page 95
3.3.3 HF Behavior and Modeling of the Extrinsic Components......Page 98
3.3.4 Non- quasi- static Behavior......Page 113
3.4.1 RF Measurement and De- embedding Techniques......Page 116
3.4.2 Parameter Extraction......Page 121
3.5 NQS MODEL FOR RF APPLICATIONS......Page 128
REFERENCES......Page 130
4.2 FLICKER NOISE MODELING......Page 134
4.2.1 The Physical Mechanisms of Flicker Noise......Page 135
4.2.2 Flicker Noise Models......Page 137
4.2.3 Future Work in Flicker Noise Modeling......Page 138
4.3.1 Existing Thermal Noise Models......Page 141
4.3.2 HF Noise Parameters......Page 143
4.3.3 Analytical Calculation of the Noise Parameters......Page 147
4.3.4 Simulation and Discussions......Page 149
REFERENCES......Page 153
5.1 INTRODUCTION......Page 156
5.2 BASIC TERMINOLOGY......Page 157
5.3 NONLINEARITIES IN CMOS DEVICES AND THEIR MODELING......Page 160
5.4 CALCULATION OF DISTORTION IN ANALOG CMOS CIRCUITS......Page 164
REFERENCES......Page 166
6.2 GATE DIELECTRIC MODEL......Page 168
6.3 ENHANCED MODELS FOR EFFECTIVE DC AND AC CHANNEL LENGTH AND WIDTH......Page 170
6.4.1 Enhanced Model for Nonuniform Lateral Doping due to Pocket ( Halo) Implant......Page 172
6.4.2 Improved Models for Short- channel Effects......Page 174
6.4.3 Model for Narrow Width Effects......Page 176
6.4.4 Complete Threshold Voltage Model in BSIM4......Page 178
6.5 CHANNEL CHARGE MODEL......Page 179
6.6 MOBILITY MODEL......Page 182
6.7 SOURCE/ DRAIN RESISTANCE MODEL......Page 184
6.8.1 I ¨C V Model When rdsMod = 0 ( RDS( V   = 0)......Page 187
6.8.2 I ¨C V Model When rdsMod = 1( RDS( V = 0)......Page 190
6.9.1 Gate- to- substrate Tunneling Current IGB......Page 191
6.9.2 Gate- to- channel and Gate- to- S/ D Currents......Page 193
6.10.1 Model for Substrate Current due to Impact Ionization of Channel Current......Page 194
6.11 CAPACITANCE MODELS......Page 195
6.11.1 Intrinsic Capacitance Models......Page 196
6.11.2 Fringing/ Overlap Capacitance Models......Page 203
6.12.1 The Transient NQS Model......Page 205
6.13.1 Gate Electrode and Intrinsic- input Resistance ( IIR) Model......Page 207
6.14 NOISE MODEL......Page 209
6.14.1 Flicker Noise Models......Page 210
6.14.2 Channel Thermal Noise Model......Page 211
6.14.3 Other Noise Models......Page 212
6.15.1 Junction Diode I ¨C V Model......Page 213
6.15.2 Junction Diode Capacitance Model......Page 215
6.16.1 Effective Junction Perimeter and Area......Page 216
6.16.2 Source/ drain Diffusion Resistance Calculation......Page 219
REFERENCES......Page 221
7.2 MODEL FEATURES......Page 224
7.3 LONG- CHANNEL DRAIN CURRENT MODEL......Page 225
7.4.1 Velocity Saturation and Channel- length Modulation......Page 227
7.4.3 Effects of Charge- sharing......Page 228
7.5 SPICE EXAMPLE: THE EFFECT OF CHARGE- SHARING......Page 229
7.6 MODELING OF CHARGE STORAGE EFFECTS......Page 231
7.7 NON- QUASI- STATIC MODELING......Page 233
7.9 TEMPERATURE EFFECTS......Page 234
REFERENCES......Page 235
8.2 MOS MODEL 9......Page 238
8.2.1 The Drain Current Model......Page 239
8.2.2 Temperature and Geometry Dependencies......Page 242
8.2.3 The Intrinsic Charge Storage Model......Page 246
8.2.4 The Noise Model......Page 248
8.3.1 The Uni . ed Charge Control Model......Page 250
8.3.2 Uni . ed MOSFET I ¨C V Model......Page 252
REFERENCES......Page 256
9.3 MODELING THE PARASITIC BJT......Page 258
9.3.1 The Ideal Diode Equation......Page 260
9.3.2 Nonideal Effects......Page 261
REFERENCES......Page 262
10.2 RESISTORS......Page 264
10.2.1 Well Resistors......Page 266
10.2.3 Diffused Resistors......Page 267
10.2.4 Poly Resistors......Page 268
10.3 CAPACITORS......Page 269
10.3.1 Poly ¨C poly Capacitors......Page 270
10.3.2 Metal ¨C insulator ¨C metal Capacitors......Page 271
10.3.3 MOSFET Capacitors......Page 272
10.3.4 Junction Capacitors......Page 273
10.4 INDUCTORS......Page 275
REFERENCES......Page 277
11.1 INTRODUCTION......Page 278
11.2.1 The In . uence of LPVM on Resistors......Page 279
11.2.2 The In . uence of LPVM on Capacitors......Page 281
11.2.3 The In . uence of LPVM on MOS Transistors......Page 284
11.3.2 Mismatching Model of Capacitors......Page 286
11.3.3 Mismatching Models of MOSFETs......Page 288
REFERENCES......Page 292
12.2 MOTIVATION......Page 294
12.3 BENCHMARK CIRCUITS......Page 296
12.3.1 Leakage Currents......Page 297
12.3.2 Transfer Characteristics in Weak and Moderate Inversion......Page 298
12.3.3 Gate Leakage Current......Page 299
12.4 AUTOMATION OF THE TESTS......Page 300
REFERENCES......Page 301
Index......Page 302