Design of Energy-Efficient Application-Specific Instruction Set Processors (ASIPs)

Team DDU......Page 1
Contents......Page 6
Acknowledgments......Page 12
About the Authors......Page 13
Foreword......Page 14
List of Figures......Page 16
List of Tables......Page 20
1 Introduction......Page 22
2.1 Focus of This Work......Page 26
2.2.1 ASIP Design Methodologies......Page 27
2.2.2 ASIP Case Studies......Page 31
2.2.3 Basic Low-Power Design Techniques......Page 32
2.2.4 Veri.cation......Page 35
2.3 Differences to Previous Work......Page 36
3.1 Metrics of the Implementation and the Hardware Design Methodology......Page 38
3.1.1 Characteristics of the Implementation......Page 39
3.1.2 Characteristics of the Design Methodology......Page 41
3.2 Basics of Low-Energy Hardware Design......Page 43
3.2.1 Sources of CMOS Energy Consumption......Page 44
3.2.2 Basic Principles of Lowering the Power Consumption......Page 47
3.2.3 Measuring and Quantifying Energy-Ef.ciency......Page 49
3.3 Techniques to Reduce the Energy Consumption......Page 53
3.3.1 System and Architecture Level......Page 54
3.3.2 Register Transfer and Logic Level......Page 57
3.3.3 Physical Level......Page 61
3.4 Concluding Remarks......Page 62
4.1 De.nitions of ASIP Related Terms......Page 64
4.2 ASIP Applications......Page 67
4.3 ASIP Design Space......Page 69
4.3.1 Functional Units......Page 72
4.3.2 Storage elements......Page 73
4.3.3 Pipelining......Page 74
4.3.4 Interconnection Structure......Page 76
4.3.5 Control Mechanisms......Page 77
4.3.6 Storage Access......Page 79
4.3.7 Instruction Coding and Instruction Fetch Mechanisms......Page 80
4.3.8 Interface Mechanisms......Page 82
4.3.9 Tightly-Coupled ASIP Accelerators......Page 85
4.4.1 Timing and Computational Performance......Page 86
4.4.2 Energy Consumption......Page 89
4.4.3 Implementation Area......Page 94
4.5 Concluding Remarks......Page 95
5 The ASIP Design Flow......Page 96
5.1 Example Applications......Page 97
5.2.1 Stimulus Generation for Application Pro.ling......Page 101
5.2.2 Application Pro.ling......Page 102
5.2.3 HW/SW Partitioning......Page 108
5.2.4 ASIP Class Selection......Page 110
5.3 Combined ASIP HW/SW Synthesis and Pro.ling......Page 114
5.3.1 ASIP Interface De.nition......Page 115
5.3.2 ASIP ISA De.nition......Page 117
5.3.3 Software Implementation and Tools......Page 118
5.3.4 Hardware Implementation and Logic Synthesis......Page 120
5.3.5 Implementation Pro.ling and Worst Case Runtime Analysis......Page 121
5.3.6 Iterative ASIP Optimization......Page 123
5.3.7 De.nition of a tightly coupled ASIP Accelerator......Page 130
5.4 Veri.cation......Page 132
5.5 Concluding Remarks......Page 137
6.1 The LISA Language......Page 138
6.2 The LISA Design Environment......Page 144
6.3.1 Instruction Encoding and Decoder Generation......Page 146
6.3.1.1 Minimization of the instruction width......Page 148
6.3.1.2 Minimization of the Toggle Activity......Page 152
6.3.2 Semi-Automatic Test Case Generation......Page 159
6.4 Concluding Remarks......Page 164
7.1 Case Study I: DVB-T Acquisition and Tracking......Page 166
7.1.1 Application Pro.ling and ASIP Class Selection......Page 168
7.1.2.1 Example 1: Saturation......Page 170
7.1.2.2 Example 2: CORDIC......Page 172
7.1.3 Overall Energy Optimization Results......Page 174
7.2 Case Study II: Linear Algebra Kernels and Eigenvalue Decomposition......Page 177
7.2.1 Implementation I: Optimized ASIP with Accelerator......Page 178
7.2.2 Implementation II: Compiler-Programmed Parameterizable Core with Accelerator......Page 182
7.2.3 Evaluation Results......Page 184
7.3 Concluding Remarks......Page 186
8 Summary......Page 188
A.1 The LISA 2.0 Language......Page 192
A.2 Design Space Exploration......Page 194
A.3 Design Implementation......Page 196
A.4.1 Compiler Generation......Page 198
A.4.2 Assembler and Linker Generation......Page 199
A.4.3 Simulator Generation......Page 200
A.4.3.3 Just-In-Time Cache Compiled Simulation (JIT-CCS)......Page 202
A.5 System Integration......Page 204
A.6 Summary......Page 205
B.1 The CORDIC Algorithm......Page 206
B.2 FIR Filter......Page 208
B.4 Vector/Matrix Operations......Page 209
B.5 Complex EVD using a Jacobi-like Algorithm......Page 211
C.2 Pipeline Organization......Page 214
C.3 Instruction Summary......Page 219
C.4 Exceptions to the Hidden Pipeline Model......Page 223
C.6 Instruction Coding......Page 224
D Different ICORE Pipeline Organizations......Page 226
E.1 Generic Register File Entity......Page 228
E.2 Generic Bit-Manipulation Unit......Page 230
F Area, Power and Design Time for ICORE......Page 234
G Acronyms......Page 238
Bibliography......Page 242