Design and Analysis of High Efficiency Line Drivers for xDSL

Team DDU......Page 1
Contents......Page 8
List of......Page 15
List of......Page 21
1. INTRODUCTION......Page 24
1.1.1 The Market......Page 25
1.1.3 Line Drivers : the gap in the xDSL system......Page 26
1.2 Power Amplifiers in CMOS......Page 28
1.3 Non-linear System Design......Page 29
2 Organisation of the Book......Page 30
2. TRADITIONAL XDSL LINE DRIVERS......Page 32
1.1 The Beginning......Page 33
1.2 Cable Technology......Page 35
1.3 Voice-Band Modem Technologies......Page 36
1.4.1 The early beginning : ISDN......Page 40
1.4.2 The further evolution to xDSL......Page 41
1.5 The Competition......Page 45
2.2 Channel Properties......Page 47
2.3.1 Bridged Taps......Page 50
2.3.2 Cross-Talk......Page 51
2.3.3 Ingress and Egress......Page 52
3.1 The Shannon Limit......Page 53
3.2.1 Basic Properties......Page 54
3.2.2 Time Domain Representation - The Crest Factor......Page 55
3.3.1 Missing Tone Power Ratio and Missing Band Depth......Page 57
3.3.2 Spectral Masks......Page 59
4.1 The Challenge......Page 60
4.2 Line Termination and The Hybrid......Page 61
5.1.1 Class AB operation......Page 64
5.1.2 Quiescent current control......Page 66
5.2 Class G/H......Page 68
5.3.1 Basic Class D configuration......Page 71
5.3.2 Output Stage Considerations......Page 72
5.3.3 Modulation Schemes......Page 74
5.3.4 Self-Oscillating Class D......Page 76
5.4 Class K and other combined structures......Page 77
6 Conclusions......Page 79
1.1 A Signal Point-of-view......Page 80
1.2 Linear versus Non-Linear......Page 81
1.3 Hard- versus Soft-Non-Linearity......Page 82
1.4 Solution Methods......Page 83
2.2 Unified Theory of the Describing Function Method......Page 84
2.4.1 Calculation......Page 86
2.4.2 Use of the single sinusoid DF......Page 88
2.4.3 The Modified Nyquist Plot......Page 89
2.4.4 Important Describing Functions......Page 90
2.5.1 Calculation......Page 91
2.5.2 Use of the TSIDF......Page 92
2.5.3 Some important TSIDF functions......Page 93
3 Conclusions......Page 95
4. BEHAVIOURAL MODELLING OF THE SOPA......Page 98
1.1 General Description......Page 99
1.2 State-Space Equations......Page 100
1.3 Numerical Verification......Page 102
2.1.1 Analytical determination......Page 104
2.1.2 Graphical representation......Page 106
2.2.1 Resistive Coupling......Page 108
2.2.2 Non-Resistive Coupling......Page 114
2.3.1 Dithering effect of the limit cycle oscillation......Page 121
2.3.2 Dynamic Range Calculation......Page 122
2.3.3 Signal Bandwidth......Page 128
2.4.1 First observations......Page 136
2.4.2 Model for the forced, coupled system......Page 139
2.5 Inherent adaptivity of limit cycle systems......Page 141
2.6 Conclusions on the analysis of the zeroth order SOPA......Page 144
3.1 Noise shaping technique......Page 145
3.2 Limit cycle oscillation......Page 146
3.3.1 Resistive Coupling......Page 150
3.3.2 Non-Resistive Coupling......Page 152
3.4.1 Dynamic Range Calculation......Page 153
3.4.2 Signal Bandwidth......Page 156
4 Final Remarks and Conclusions......Page 157
5. DESIGN PLAN AND CAD-TOOLS......Page 160
1 Design plan synthesis......Page 161
1.1.1 Limitations imposed by the processing technology......Page 162
1.1.2 Transformer Limitations......Page 165
1.2.1 Output Swing Estimation......Page 167
1.2.2 SOPA order estimation......Page 168
1.2.4 Power estimation......Page 169
2.1 Requirements......Page 171
2.2.1 Framework Overview......Page 172
2.2.2 Parameter structures......Page 174
2.3.2 Numerical implementation of the describing function model......Page 175
2.3.3 Graphical frequency domain analysis......Page 177
2.4.1 ODEPACK implementation......Page 178
2.4.2 Hspice/Eldo Simulations......Page 181
2.4.3 Comparison between numerical methods......Page 183
2.5 Measurement Interfaces......Page 184
2.5.2 Equipment interfaces and post-processing......Page 185
3 Conclusions......Page 186
6. REALISATIONS IN MAINSTREAM CMOS......Page 190
1.1 Goal of the Test Chip......Page 191
1.2.1 The Output Driver......Page 192
1.2.2 The Tapered Buffer......Page 193
1.2.3 The Comparator......Page 194
1.2.4 The Loop Filter......Page 198
1.3.2 Electro-migration......Page 200
1.3.3 Other Considerations......Page 203
1.4.2 Sine wave inputs......Page 205
1.5.1 Comparison with the state-of-the-art......Page 209
1.5.2 Strong Points......Page 210
2.1 Goal of the Test Chip......Page 212
2.2.2 The Tapered Buffer......Page 214
2.2.3 The Comparator......Page 215
2.2.4 The Integrators......Page 216
2.4.1 Measurement Set-up......Page 218
2.4.2 ADSL Characterisation......Page 220
2.4.4 FTTEx Deployment......Page 221
2.5.1 Comparison with the present state-of-the-art......Page 222
2.5.2 Strong Points......Page 223
3 Conclusions......Page 225
1.1 To build a highly efficient line driver for ADSL......Page 228
1.3 This work advances the knowledge of non-linear analogue design......Page 231
Glossary......Page 234
1 Stability Criterion......Page 242
2 Polar Form of the Coupled Open Loop Transfer Function......Page 243
3 Calculation of the Stability Conditions......Page 244
References......Page 248
Index......Page 254