Cryptographic Hardware and Embedded Systems – CHES 2011: 13th International Workshop, Nara, Japan, September 28 – October 1, 2011. Proceedings

Front Matter....Pages -
An Exploration of Mechanisms for Dynamic Cryptographic Instruction Set Extension....Pages 1-16
FPGA-Based True Random Number Generation Using Circuit Metastability with Adaptive Feedback Control....Pages 17-32
Generic Side-Channel Countermeasures for Reconfigurable Devices....Pages 33-48
Improved Collision-Correlation Power Analysis on First Order Protected AES....Pages 49-62
Higher-Order Glitches Free Implementation of the AES Using Secure Multi-party Computation Protocols....Pages 63-78
Protecting AES with Shamir’s Secret Sharing Scheme....Pages 79-94
A Fast and Provably Secure Higher-Order Masking of AES S-Box....Pages 95-107
Software Implementation of Binary Elliptic Curves: Impact of the Carry-Less Multiplier on Scalar Multiplication....Pages 108-123
High-Speed High-Security Signatures....Pages 124-142
To Infinity and Beyond: Combined Attack on ECC Using Points of Low Order....Pages 143-159
Random Sampling for Short Lattice Vectors on Graphics Cards....Pages 160-175
Extreme Enumeration on GPU and in Clouds....Pages 176-191
Modulus Fault Attacks against RSA-CRT Signatures....Pages 192-206
Breaking Mifare DESFire MF3ICD40: Power Analysis and Templates in the Real World....Pages 207-222
Information Theoretic and Security Analysis of a 65-Nanometer DDSLL AES S-Box....Pages 223-239
Thwarting Higher-Order Side Channel Analysis with Additive and Multiplicative Maskings....Pages 240-255
Extractors against Side-Channel Attacks: Weak or Strong?....Pages 256-272
Standardization Works for Security Regarding the Electromagnetic Environment....Pages 273-273
Meet-in-the-Middle and Impossible Differential Fault Analysis on AES....Pages 274-291
On the Power of Fault Sensitivity Analysis and Collision Side-Channel Attacks in a Combined Setting....Pages 292-311
 spongent : A Lightweight Hash Function....Pages 312-325
The LED Block Cipher....Pages 326-341
 Piccolo : An Ultra-Lightweight Blockcipher....Pages 342-357
Lightweight and Secure PUF Key Storage Using Limits of Machine Learning....Pages 358-373
Recyclable PUFs: Logically Reconfigurable PUFs....Pages 374-389
Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches....Pages 390-406
MECCA: A Robust Low-Overhead PUF Using Embedded Memory Array....Pages 407-420
FPGA Implementation of Pairings Using Residue Number System and Lazy Reduction....Pages 421-441
High Speed Cryptoprocessor for η T Pairing on 128-bit Secure Supersingular Elliptic Curves over Characteristic Two Fields....Pages 442-458
Fast Multi-precision Multiplication for Public-Key Cryptography on Embedded Microprocessors....Pages 459-474
Small Public Keys and Fast Verification for $\\mathcal{M}$ ultivariate $\\mathcal{Q}$ uadratic Public Key Systems....Pages 475-490
Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs....Pages 491-506
Efficient Hashing Using the AES Instruction Set....Pages 507-522
Back Matter....Pages -