Computer Organization and Architecture:Designing for Performance

Cover......Page 1
Inside Front Cover......Page 2
Title Page......Page 6
Copyright Page......Page 7
Dedication......Page 8
Contents......Page 10
Foreword......Page 16
Preface......Page 18
About the Author......Page 26
Chapter 1 Basic Concepts and Computer Evolution......Page 28
1.1 Organization and Architecture......Page 29
1.2 Structure and Function......Page 30
1.3 A Brief History of Computers......Page 38
1.4 The Evolution of the Intel x86 Architecture......Page 54
1.5 Embedded Systems......Page 56
1.6 Arm Architecture......Page 60
1.7 Cloud Computing......Page 66
1.8 Key Terms, Review Questions, and Problems......Page 69
Chapter 2 Performance Issues......Page 72
2.1 Designing for Performance......Page 73
2.2 Multicore, Mics, and Gpgpus......Page 79
2.3 Two Laws that Provide Insight: Ahmdahl’s Law and Little’s Law......Page 80
2.4 Basic Measures of Computer Performance......Page 83
2.5 Calculating the Mean......Page 86
2.6 Benchmarks and Spec......Page 94
2.7 Key Terms, Review Questions, and Problems......Page 101
Chapter 3 A Top- Level View of Computer Function and Interconnection......Page 107
3.1 Computer Components......Page 108
3.2 Computer Function......Page 110
3.3 Interconnection Structures......Page 126
3.4 Bus Interconnection......Page 127
3.5 Point-to-Point Interconnect......Page 129
3.6 Pci Express......Page 134
3.7 Key Terms, Review Questions, and Problems......Page 143
Chapter 4 Cache Memory......Page 147
4.1 Computer Memory System Overview......Page 148
4.2 Cache Memory Principles......Page 155
4.3 Elements of Cache Design......Page 158
4.4 Pentium 4 Cache Organization......Page 176
4.5 Key Terms, Review Questions, and Problems......Page 179
Appendix 4A Performance Characteristics of Two- Level Memories......Page 184
Chapter 5 Internal Memory......Page 192
5.1 Semiconductor Main Memory......Page 193
5.2 Error Correction......Page 201
5.3 DDR Dram......Page 207
5.4 Flash Memory......Page 212
5.5 Newer Nonvolatile Solid-State Memory Technologies......Page 214
5.6 Key Terms, Review Questions, and Problems......Page 217
Chapter 6 External Memory......Page 221
6.1 Magnetic Disk......Page 222
6.2 Raid......Page 231
6.3 Solid State Drives......Page 239
6.4 Optical Memory......Page 244
6.5 Magnetic Tape......Page 249
6.6 Key Terms, Review Questions, and Problems......Page 251
Chapter 7 Input/Output......Page 255
7.1 External Devices......Page 257
7.2 I/O Modules......Page 259
7.3 Programmed I/O......Page 262
7.4 Interrupt-Driven I/O......Page 266
7.5 Direct Memory Access......Page 275
7.6 Direct Cache Access......Page 281
7.7 I/O Channels and Processors......Page 288
7.8 External Interconnection Standards......Page 290
7.9 IBM zEnterprise EC12 I/O Structure......Page 293
7.10 Key Terms, Review Questions, and Problems......Page 297
Chapter 8 Operating System Support......Page 302
8.1 Operating System Overview......Page 303
8.2 Scheduling......Page 314
8.3 Memory Management......Page 320
8.4 Intel x86 Memory Management......Page 331
8.5 Arm Memory Management......Page 336
8.6 Key Terms, Review Questions, and Problems......Page 341
Chapter 9 Number Systems......Page 345
9.1 The Decimal System......Page 346
9.2 Positional Number Systems......Page 347
9.4 Converting Between Binary and Decimal......Page 348
9.5 Hexadecimal Notation......Page 351
9.6 Key Terms and Problems......Page 353
Chapter 10 Computer Arithmetic......Page 355
10.1 The Arithmetic and Logic Unit......Page 356
10.2 Integer Representation......Page 357
10.3 Integer Arithmetic......Page 362
10.4 Floating- Point Representation......Page 377
10.5 Floating-Point Arithmetic......Page 385
10.6 Key Terms, Review Questions, and Problems......Page 394
Chapter 11 Digital Logic......Page 399
11.1 Boolean Algebra......Page 400
11.2 Gates......Page 403
11.3 Combinational Circuits......Page 405
11.4 Sequential Circuits......Page 423
11.5 Programmable Logic Devices......Page 432
11.6 Key Terms and Problems......Page 436
Chapter 12 Instruction Sets: Characteristics and Functions......Page 439
12.1 Machine Instruction Characteristics......Page 440
12.2 Types of Operands......Page 447
12.3 Intel x86 and ARM Data Types......Page 449
12.4 Types of Operations......Page 452
12.5 Intel x86 and ARM Operation Types......Page 465
12.6 Key Terms, Review Questions, and Problems......Page 473
Appendix 12A Little-, Big-, and Bi-Endian......Page 479
Chapter 13 Instruction Sets: Addressing Modes and Formats......Page 483
13.1 Addressing Modes......Page 484
13.2 x86 and ARM Addressing Modes......Page 490
13.3 Instruction Formats......Page 496
13.4 x86 and ARM Instruction Formats......Page 504
13.5 Assembly Language......Page 509
13.6 Key Terms, Review Questions, and Problems......Page 511
Chapter 14 Processor Structure and Function......Page 515
14.1 Processor Organization......Page 516
14.2 Register Organization......Page 518
14.3 Instruction Cycle......Page 523
14.4 Instruction Pipelining......Page 527
14.5 The x86 Processor Family......Page 544
14.6 The ARM Processor......Page 551
14.7 Key Terms, Review Questions, and Problems......Page 557
Chapter 15 Reduced Instruction Set Computers......Page 562
15.1 Instruction Execution Characteristics......Page 564
15.2 The Use of a Large Register File......Page 569
15.3 Compiler-Based Register Optimization......Page 574
15.4 Reduced Instruction Set Architecture......Page 576
15.5 RISC Pipelining......Page 582
15.6 MIPS R4000......Page 586
15.7 SPARC......Page 592
15.8 RISC versus CISC Controversy......Page 597
15.9 Key Terms, Review Questions, and Problems......Page 598
Chapter 16 Instruction-Level Parallelism and Superscalar Processors......Page 602
16.1 Overview......Page 603
16.2 Design Issues......Page 608
16.3 Intel Core Microarchitecture......Page 618
16.4 ARM Cortex-A8......Page 623
16.5 ARM Cortex-M3......Page 631
16.6 Key Terms, Review Questions, and Problems......Page 635
Chapter 17 Parallel Processing......Page 640
17.1 Multiple Processor Organizations......Page 642
17.2 Symmetric Multiprocessors......Page 644
17.3 Cache Coherence and the MESI Protocol......Page 648
17.4 Multithreading and Chip Multiprocessors......Page 655
17.5 Clusters......Page 660
17.6 Nonuniform Memory Access......Page 667
17.7 Cloud Computing......Page 670
17.8 Key Terms, Review Questions, and Problems......Page 677
Chapter 18 Multicore Computers......Page 683
18.1 Hardware Performance Issues......Page 684
18.2 Software Performance Issues......Page 687
18.3 Multicore Organization......Page 692
18.4 Heterogeneous Multicore Organization......Page 694
18.5 Intel Core i7-990X......Page 703
18.6 ARM Cortex-A15 MPCore......Page 704
18.7 IBM zEnterprise EC12 Mainframe......Page 709
18.8 Key Terms, Review Questions, and Problems......Page 712
Chapter 19 General-Purpose Graphic Processing Units......Page 715
19.1 Cuda Basics......Page 716
19.2 GPU versus CPU......Page 718
19.3 GPU Architecture Overview......Page 719
19.4 Intel’s Gen8 GPU......Page 728
19.5 When to Use a GPU as a Coprocessor......Page 731
19.6 Key Terms and Review Questions......Page 733
Chapter 20 Control Unit Operation......Page 734
20.1 Micro-Operations......Page 735
20.2 Control of the Processor......Page 741
20.3 Hardwired Implementation......Page 751
20.4 Key Terms, Review Questions, and Problems......Page 754
Chapter 21 Microprogrammed Control......Page 756
21.1 Basic Concepts......Page 757
21.2 Microinstruction Sequencing......Page 766
21.3 Microinstruction Execution......Page 772
21.4 TI 8800......Page 782
21.5 Key Terms, Review Questions, and Problems......Page 793
Appendix A Projects for Teaching Computer Organization and Architecture......Page 795
A.1 Interactive Simulations......Page 796
A.3 Simulation Projects......Page 798
A.4 Assembly Language Projects......Page 799
A.7 Test Bank......Page 800
Appendix B Assembly Language and Related Topics......Page 801
B.1 Assembly Language......Page 802
B.2 Assemblers......Page 810
B.3 Loading and Linking......Page 814
B.4 Key Terms, Review Questions, and Problems......Page 822
References......Page 827
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Credits......Page 860