Computer Engineering and Technology: 17th CCF Conference, NCCET 2013, Xining, China, July 20-22, 2013. Revised Selected Papers

Front Matter....Pages -
Design and Implementation of a Novel Entirely Covered K 2 CORDIC....Pages 1-8
The Analysis of Generic SIMT Scheduling Model Extracted from GPU....Pages 9-18
A Unified Cryptographic Processor for RSA and ECC in RNS....Pages 19-32
Real-Time Implementation of 4x4 MIMO-OFDM System for 3GPP-LTE Based on a Programmable Processor....Pages 33-43
A Market Data Feeds Processing Accelerator Based on FPGA....Pages 44-52
The Design of Video Accelerator Bus Wrapper....Pages 53-60
Design and Implementation of Novel Flexible Crypto Coprocessor and Its Application in Security Protocol....Pages 61-72
Wormhole Bubble in Torus Networks....Pages 73-80
Self-adaptive Scheme to Adjust Redundancy for Network Coding with TCP....Pages 81-91
Research on Shifter Based on iButterfly Network....Pages 92-100
A Highly-Efficient Approach to Adaptive Load Balance for Scalable TBGP....Pages 101-110
OpenACC to Intel Offload: Automatic Translation and Optimization....Pages 111-120
Applying Variable Neighborhood Search Algorithm to Multicore Task Scheduling Problem....Pages 121-130
Empirical Analysis of Human Behavior Patterns in BBS....Pages 131-142
Performance Evaluation and Scalability Analysis of NPB-MZ on Intel Xeon Phi Coprocessor....Pages 143-152
An Effective Framework of Program Optimization for High Performance Computing....Pages 153-162
A Constant Loop Bandwidth Fraction-N Frequency Synthesizer for GNSS Receivers....Pages 163-170
Investigation of Reproducibility and Repeatability Issue on EFT Test at IC Level to Microcontrollers....Pages 171-179
A Scan Chain Based SEU Test Method for Microprocessors....Pages 180-185
Achieving Predictable Performance in SMT Processors by Instruction Fetch Policy....Pages 186-197
Reconfigurable Many-Core Processor with Cache Coherence....Pages 198-207
Backhaul-Route Pre-Configuration Mechanism for Delay Optimization in NoCs....Pages 208-217
A Novel CGRA Architecture and Mapping Algorithm for Application Acceleration....Pages 218-227
Tunable Negative Differential Resistance of Single-Electron Transistor Controlled by Capacitance....Pages 228-234
Modeling and Electrical Simulations of Thin-Film Gated SOI Lateral PIN Photodetectors for High Sensitivity and Speed Performances....Pages 235-243
A Full Adder Based on Hybrid Single-Electron Transistors and MOSFETs at Room Temperature....Pages 244-250
Back Matter....Pages -