Computer Architecture: A Quantitative Approach, 2nd Edition, 1996

1. 
Fundamentals of
 Computer Design......Page 1
1.1 
Introduction......Page 2
1.2 
The Task of a Computer Designer......Page 4
1.3 
Technology and Computer Usage Trends......Page 7
1.4
 Cost and Trends in Cost......Page 9
1.5 Measuring and Reporting Performance......Page 19
1.6 Quantitative Principles of Computer Design......Page 30
1.7 Putting It All Together:
 The Concept of Memory Hierarchy......Page 40
1.8 Fallacies and Pitfalls......Page 45
1.9 Concluding Remarks......Page 52
1.10 Historical Perspective and References......Page 54
- References......Page 60
- Exercises......Page 61
2. Instruction Set 
Principles and
 Examples......Page 69
2.1 
Introduction......Page 70
2.2 
Classifying Instruction Set Architectures......Page 71
2.3 
Memory Addressing......Page 74
2.4 Operations in the Instruction Set......Page 81
2.5 Type and Size of Operands......Page 86
2.6 Encoding an Instruction Set......Page 88
2.7 Crosscutting Issues: The Role of Compilers......Page 90
2.8 Putting It All Together: The DLX Architecture......Page 97
2.9 Fallacies and Pitfalls......Page 109
2.10 Concluding Remarks......Page 112
2.11 Historical Perspective and References......Page 113
- References......Page 118
- Exercises......Page 119
3. 
Pipelining......Page 125
3.1
 What Is Pipelining?......Page 126
3.2
 The Basic Pipeline for DLX......Page 133
3.3 The Major Hurdle of Pipelining.
Pipeline Hazards......Page 140
3.4 Data Hazards......Page 147
3.5 Control Hazards......Page 162
3.6 What Makes Pipelining Hard to Implement?......Page 179
3.7 Extending the DLX Pipeline to
 Handle Multicycle Operations......Page 188
3.8 Crosscutting Issues: 
Instruction Set Design and Pipelining......Page 200
3.9 Putting It All Together:
 The MIPS R4000 Pipeline......Page 202
3.10 Fallacies and Pitfalls......Page 210
3.11 Concluding Remarks......Page 212
3.12 Historical Perspective and References......Page 213
- References......Page 214
- Exercises......Page 215
4. 
Advanced Pipelining 
and Instruction-
Level Parallelism
......Page 221
4.1 
Instruction-Level Parallelism: 
Concepts and Challenges......Page 222
4.2 Overcoming Data Hazards
 with Dynamic Scheduling......Page 241
4.3 Reducing Branch Penalties
 with Dynamic Hardware Prediction......Page 263
4.4 Taking Advantage of More ILP 
with Multiple Issue......Page 279
4.5 Compiler Support for Exploiting ILP......Page 290
4.6 Hardware Support for Extracting 
More Parallelism......Page 300
4.7 Studies of ILP......Page 319
4.8 Putting It All Together: The PowerPC 620......Page 336
4.9 Fallacies and Pitfalls......Page 350
4.10 Concluding Remarks......Page 353
4.11 Historical Perspective and References......Page 355
- References......Page 361
- Exercises......Page 363
5. 
Memory-Hierarchy
 Design......Page 372
5.1 
Introduction......Page 373
5.2 
The ABCs of Caches......Page 375
5.3 Reducing Cache Misses......Page 390
5.4 Reducing Cache Miss Penalty......Page 411
5.5 Reducing Hit Time......Page 422
5.6 Main Memory......Page 427
5.7 Virtual Memory......Page 439
5.8 Protection and Examples of Virtual Memory......Page 447
5.9 Crosscutting Issues in the Design of 
Memory Hierarchies......Page 457
5.10 Putting It All Together: 
The Alpha AXP 21064 Memory Hierarchy......Page 461
5.11 Fallacies and Pitfalls......Page 466
5.12 Concluding Remarks......Page 471
5.13 Historical Perspective and References......Page 472
- References......Page 474
- Exercises......Page 476
6. 
Storage Systems......Page 484
6.1 
Introduction......Page 485
6.2 
Types of Storage Devices......Page 486
6.3 
Buses.Connecting I/O Devices to CPU/Memory......Page 496
6.4 I/O Performance Measures......Page 504
6.5 Reliability, Availability, and RAID......Page 521
6.6 Crosscutting Issues: 
Interfacing to an Operating System......Page 525
6.7 Designing an I/O System......Page 528
6.8 Putting It All Together: 
UNIX File System Performance......Page 539
6.9 Fallacies and Pitfalls......Page 548
6.11 Historical Perspective and References......Page 553
- References......Page 555
- Exercises......Page 557
7. 
Interconnection 
Networks......Page 562
7.1 
Introduction......Page 563
7.2 
A Simple Network......Page 565
7.3
 Connecting the Interconnection Network 
to the Computer......Page 573
7.4 
Interconnection Network Media......Page 576
7.5 Connecting More Than Two Computers......Page 579
7.6 Practical Issues for Commercial
 Interconnection Networks......Page 597
7.7 Examples of Interconnection Networks......Page 601
7.8 Crosscutting Issues for 
Interconnection Networks......Page 605
7.9 Internetworking......Page 608
7.10 Putting It All Together:
 An ATM Network of Workstations......Page 613
7.11 Fallacies and Pitfalls......Page 622
7.12 Concluding Remarks......Page 625
7.13 Historical Perspective and References......Page 626
- Exercises......Page 629
8. 
Multiprocessors......Page 633
8.1 
Introduction......Page 634
8.2
 Characteristics of Application Domains......Page 646
8.3 Centralized Shared-Memory Architectures......Page 653
8.4 Distributed Shared-Memory Architectures......Page 676
8.5 Synchronization......Page 693
8.6 Models of Memory Consistency......Page 707
8.7 Crosscutting Issues......Page 720
8.8 Putting It All Together:
 The SGI Challenge Multiprocessor......Page 727
8.9 Fallacies and Pitfalls......Page 733
8.10 Concluding Remarks......Page 739
8.11 Historical Perspective and References......Page 744
- References......Page 752
- Exercises......Page 754
A. 
Computer Arithmetic......Page 760
A.1 
Introduction......Page 761
A.2
 Basic Techniques of Integer Arithmetic......Page 762
A.3 Floating Point......Page 773
A.4 Floating-Point Multiplication......Page 777
A.5 Floating-Point Addition......Page 782
A.6 Division and Remainder......Page 788
A.7 More on Floating-Point Arithmetic......Page 794
A.8 Speeding Up Integer Addition......Page 798
A.9 Speeding Up Integer Multiplication and Division......Page 806
A.10 Putting It All Together......Page 821
A.11 Fallacies and Pitfalls......Page 825
A.12 Historical Perspective and References......Page 826
- References......Page 829
- Exercises......Page 832
B
. Vector Processors......Page 838
B.1 
Why Vector Processors?......Page 839
B.2
 Basic Vector Architecture......Page 841
B.3 Two Real-World Issues: 
Vector Length and Stride......Page 853
B.4 Effectiveness of Compiler Vectorization......Page 860
B.5 Enhancing Vector Performance......Page 861
B.6 Putting It All Together:
 Performance of Vector Processors......Page 867
B.7 Fallacies and Pitfalls......Page 873
B.8 Concluding Remarks......Page 875
B.9 Historical Perspective and References......Page 876
- References......Page 879
- Exercises......Page 881
C. 
Survey of RISC 
Architectures
......Page 886
C.1 
Introduction......Page 887
C.2 
Addressing Modes and Instruction Formats......Page 889
C.3 
Instructions: The DLX Subset......Page 891
C.4 Instructions: Common Extensions to DLX......Page 895
C.5 Instructions Unique to MIPS......Page 899
C.6 Instructions Unique to SPARC......Page 901
C.7 Instructions Unique to PowerPC......Page 904
C.8 Instructions Unique to PA-RISC......Page 905
C.9 Concluding Remarks......Page 908
C.10 References......Page 911