Circuits at the nanoscale : communications, imaging, and sensing

CIRCUITS AT THE NANOSCALE: Communications, Imaging, and Sensing......Page 3
Contents......Page 6
Editor......Page 10
Contributors......Page 12
Part I: CMOS Technology at the Nanoscale......Page 15
1.1 CMOS RISE TO DOMINANCE: A VERY BRIEF HISTORY......Page 17
1.2 CMOS IS EVERYWHERE......Page 18
1.3 LOGIC-BASED EMBEDDED DRAM CMOS......Page 20
1.5 HIGH-VOLTAGE CMOS......Page 21
1.8.2 MEMS......Page 22
REFERENCES......Page 23
2.1 INTRODUCTION: TWO DIRECTIONS FOR TECHNOLOGY DEVELOPMENT......Page 25
2.2.1 LITHOGRAPHY AND OPC: CLOSING THE SUBWAVELENGTH GAP......Page 26
2.2.2 MOSFETS......Page 27
2.3.1 PROCESS CHALLENGES......Page 29
2.3.2 VARIABILITY REDUCTION FORMOSFETS AND PASSIVE ELEMENTS......Page 30
REFERENCES......Page 37
3.1.1 CHARACTERIZATION OF VARIATIONS......Page 39
3.1.2 LITHOGRAPHY-INDUCED VARIATIONS......Page 41
3.2 TEST CHIP......Page 42
3.3.1 EFFECTS OF LAYOUT ON FREQUENCY AND LEAKAGE......Page 45
3.3.2 D2D VARIATIONS......Page 47
3.3.4 INFERRING PROCESS PARAMETERS......Page 48
REFERENCES......Page 50
4.1 INTRODUCTION......Page 53
4.2 WAFER-LEVEL 3D TECHNOLOGY PLATFORMS......Page 54
4.3 DIGITAL IC APPLICATIONS......Page 58
4.4 ANALOG/MIXED-SIGNAL APPLICATIONS......Page 60
4.5 UNIQUE SYSTEM ARCHITECTURES......Page 61
4.6 FUTURE DRIVERS FOR WAFER-LEVEL 3D IN IC MANUFACTURING......Page 63
4.6.4 INDUSTRY INFRASTRUCTURE DRIVERS......Page 64
REFERENCES......Page 65
5.1 BACKGROUND AND FUTURE TRENDS......Page 67
5.2.1 DEMANDS OF BOTH LOW-POWER AND HIGH-SPEED OPERATION......Page 68
5.2.2 DYNAMIC BODY-CONTROL TECHNIQUE......Page 69
5.2.3 AUTOMATIC SOURCE/BODY-CONTROL TECHNIQUE......Page 71
5.3.2 TTRAM CELLOPERATION......Page 73
5.3.3 TTRAM ARRAY ARCHITECTURE......Page 76
5.3.5 SCALABLE FUNCTIONS OF TTRAM......Page 80
5.3.6 ACTIVELY BODY-BIAS CONTROLLED SRAM......Page 83
5.4 FEATURE SOI TECHNOLOGY TREND......Page 84
REFERENCES......Page 86
6.1 INTRODUCTION......Page 89
6.2 SiGe DEVICES: THE BASICS......Page 90
6.4 SiGe PERFORMANCE ROADMAP......Page 91
6.5 MODERN SiGe BiCMOS RF PLATFORM......Page 94
6.6.1 KEYWIRELESS RF CIRCUIT BLOCKS: LOW-NOISE AMPLIFIER......Page 97
6.6.2 KEYWIRELESS RF CIRCUIT BLOCKS: POWER AMPLIFIER......Page 98
6.6.3 EMERGING APPLICATIONS......Page 102
REFERENCES......Page 105
Part II: Emerging Design Techniques......Page 107
7.1 INTRODUCTION......Page 109
7.2 WHAT IS FLICKER NOISE?......Page 110
7.2.1 THE NATURE OF FLICKER NOISE......Page 111
7.2.3 MEMORIES INMOSFETS ANDOTHER ELECTRONIC DEVICES......Page 112
7.3 SWITCHED-CAPACITOR TECHNIQUES......Page 114
7.3.1 SAMPLED NOISE IN SC CIRCUITS......Page 116
7.4 BIAS SWITCHING AND LARGE-SCALE EXCITATION......Page 117
7.5 CHOPPING......Page 119
7.5.1 CONVENTIONAL CHOPPER AMPLIFIER......Page 120
7.5.2 MULTIPATH CHOPPER AMPLIFIERS......Page 121
7.5.3 CHOPPING IN SAMPLED-DATA SYSTEMS......Page 122
7.6 CORRELATED DOUBLE SAMPLING AND AUTO-ZERO TECHNIQUES......Page 123
7.6.1 SWITCHED-CAPACITOR COMPARATOR WITH CDS......Page 124
7.6.2 SWITCHED-CAPACITOR AMPLIFIER WITH CDS......Page 125
7.6.4 CORRELATED DOUBLE SAMPLING COMBINED WITH LARGE-SCALE EXCITATION......Page 126
7.A1 APPENDIX......Page 127
REFERENCES......Page 128
8.1 INTRODUCTION......Page 131
8.2 SHUNT PEAKING AND BRIDGED-SHUNT PEAKING......Page 133
8.3 SERIES PEAKING......Page 134
8.4 BRIDGED-SHUNT-SERIES PEAKING......Page 136
8.5 ASYMMETRIC T-COIL PEAKING......Page 137
8.6 DESIGN OF HIGH-SPEED WIDEBAND DIFFERENTIAL AMPLIFIERS......Page 139
8.7 EFFECTS OF OTHER DEVICE PARASITICS......Page 140
8.7.1 EFFECTS OF Cgd......Page 141
8.7.2 EFFECTS OF gds......Page 142
8.8.1 MEASUREMENT METHODOLOGY......Page 143
8.8.2 MEASURED DATA......Page 144
REFERENCES......Page 146
9.1 INTRODUCTION......Page 149
9.2.1 CONFIGURATION AND CHARACTERISTICS......Page 150
9.2.2 FREQUENCY RANGE......Page 151
9.3.1 CONFIGURATION......Page 152
9.3.2 CHARACTERIZATION......Page 153
9.3.2.2 Turn Ratio......Page 154
9.3.2.4 Voltage Ratio......Page 155
9.3.3 NONIDEAL ACTIVE TRANSFORMERS......Page 156
9.3.5 CMOS ACTIVE TRANSFORMERS......Page 158
9.4 APPLICATIONS OF CMOS ACTIVE TRANSFORMERS......Page 159
REFERENCES......Page 161
10.1 INTRODUCTION......Page 163
10.2 REGISTER FILE ORGANIZATION......Page 165
10.3 BITLINE LEAKAGE ROBUSTNESS......Page 167
10.4.1 WORDLINE UNDERDRIVE LOCAL BITLINE......Page 168
10.4.3 PROCESS VARIATION COMPENSATING DYNAMIC LOCAL BITLINE......Page 169
10.5 SUMMARY......Page 170
REFERENCES......Page 171
11.1 INTRODUCTION......Page 173
11.2.2 ELECTRICAL SOLITONS......Page 175
11.2.4 FORMING AND DAMPING OF ELECTRICAL SOLITONS......Page 176
11.3.2 OSCILLATION INSTABILITYMECHANISMS......Page 178
11.3.3 TAMING ELECTRICAL SOLITONS WITH AN AMPLIFIER......Page 181
11.4 DESIGN PROCEDURE......Page 182
11.5.1 PROTOTYPE IMPLEMENTATION......Page 183
11.5.2.1 Adaptive Bias Control......Page 185
11.5.2.3 Perturbation Rejection......Page 186
11.5.2.5 Spatial Soliton Propagation in Steady State......Page 187
11.5.3.1 Existence of a Limit Cycle......Page 188
11.5.3.2 Spatial Dynamics Revisited......Page 189
11.6 SECOND PROTOTYPE—DISCRETE MICROWAVE SOLITON OSCILLATOR......Page 191
11.7.1 CHIP-SCALE IMPLEMENTATION......Page 193
11.7.2 MEASUREMENT RESULTS......Page 194
11.8 SOLITON OSCILLATOR SUMMARY AND FUTURE DIRECTIONS......Page 195
11.10 CONCLUSION......Page 196
REFERENCES......Page 197
Part III: Mixed-Signal CMOS Circuits......Page 199
12.1 DIGITAL-TO-ANALOG CONVERTER BASICS......Page 201
12.1.2 VOLTAGE DIVIDER......Page 203
12.1.4 R–2R LADDER DACS......Page 204
12.1.5 DELTA–SIGMA ARCHITECTURE......Page 205
12.2 CURRENT-MODE DACs IN CMOS......Page 206
12.3 POWER DISSIPATION......Page 207
12.4 STATIC ERRORS AND MATCHING......Page 208
12.5 SELF-CALIBRATION......Page 211
12.6 FINITE OUTPUT IMPEDANCE......Page 213
12.7 SIMILARITIES BETWEEN DAC AND FLASH ADC......Page 215
12.8 DIGITAL DATA PATTERN-DEPENDENT NOISE......Page 216
12.9 DATA-DEPENDENT CLOCK LOADING......Page 217
12.10 SWITCH GATE DRIVE......Page 219
12.12 QUAD SWITCHING/CONSTANT DATA ACTIVITY......Page 223
REFERENCES......Page 225
13.1 INTRODUCTION......Page 227
13.2 ADC PERFORMANCE SCALING......Page 228
13.3 HIGH-SPEED SUBSAMPLING AND OVERSAMPLING ADCs......Page 230
13.4.1 FLASH ADC ARCHITECTURE......Page 231
13.4.2 TIME-BASED ADC ARCHITECTURE......Page 234
13.5 HIGH-RESOLUTION AND MULTI-GHz ADC ARCHITECTURES......Page 235
REFERENCES......Page 237
14.1 INTRODUCTION......Page 239
14.2 POWER EFFICIENCY OF ADC ARCHITECTURE......Page 240
14.3 ASYNCHRONOUS PROCESSING......Page 241
14.4.1 ARCHITECTURE......Page 244
14.4.2 DYNAMIC COMPARATOR AND READY SIGNAL......Page 245
14.4.4 SERIES NONBINARY CAPACITIVE LADDER......Page 246
14.4.6 VARIABLE DUTY-CYCLED CLOCK......Page 248
14.4.8 MEASURED RESULTS......Page 250
14.5 SCALING TREND OF AN ASYNCHRONOUS ADC......Page 252
14.6 APPLICATIONS OF THE PROPOSED ADC TOPOLOGY......Page 254
REFERENCES......Page 256
15.1 INTRODUCTION......Page 259
15.2.1 IMPEDANCE SCALING......Page 260
15.2.3 FREQUENCY SCALING......Page 261
15.3 Gm–C TOPOLOGIES......Page 262
15.3.1 ARCHITECTURAL CONSIDERATIONS......Page 263
15.3.2 BUILDING BLOCKS AND NONIDEALITIES......Page 265
15.3.3 DESIGN PROCEDURE......Page 267
15.4 LC TOPOLOGIES......Page 268
15.4.1 ARCHITECTURAL CONSIDERATIONS......Page 269
15.5 EQUALIZING FILTERS......Page 270
15.5.1 BOOST FILTER ARCHITECTURE USING Gm–C TECHNIQUES......Page 272
15.5.2 BOOST FILTER ARCHITECTURE USING LC TECHNIQUES......Page 273
15.5.3 Gm–C VERSUS LC STRUCTURES......Page 275
REFERENCES......Page 278
CONTENTS......Page 281
16.1.1 SURVEY OF PUBLISHED DESIGNS......Page 282
16.1.2 CURRENT DESIGN TRENDS......Page 284
16.2.2 QUANTIZATION NOISE......Page 285
16.3.1 THEORETICAL BACKGROUND......Page 286
16.3.3 ZERO-DELAY CT BP sigmadelta MODULATORS......Page 287
16.3.4 DELAYED CT BP sigmadelta MODULATORS......Page 288
16.4.1 DESIGN ARCHITECTURE......Page 289
16.4.2 gm–C RESONATOR......Page 290
16.4.4 COMPARATOR......Page 291
16.4.5 POSTLAYOUT SIMULATION......Page 292
16.6 CT BP f sigmadelta APPLICATIONS......Page 293
16.6.1 FRACTIONALDELAY sigmadelta UPCONVERTER......Page 294
16.6.2 f sigmadelat-BASED PA......Page 296
REFERENCES......Page 297
Part IV: Circuits for Communications......Page 301
17.1 INTRODUCTION......Page 303
17.3.1 LIMITATIONS OF SINGLE-TRANSISTOR LNAS......Page 304
17.3.2 REVERSE ISOLATION ENHANCEMENT UTILIZINGMAGNETIC FEEDBACK......Page 305
17.3.3 TRIPLE TRANSFORMER LNA ANALYSIS......Page 307
17.3.3.2 Multiple Transformer Layout......Page 309
17.3.4 ALTERNATIVEMETHOD FOR REVERSE ISOLATION ENHANCEMENT......Page 310
17.4 LNA LINEARIZATION UTILIZING MAGNETIC FEEDBACK......Page 316
17.4.1.1 Shunt Transistor Predistorter......Page 317
17.4.1.2 Proposed Predistortion Scheme......Page 318
17.5 LOW-VOLTAGE MIXER DESIGN......Page 323
17.5.1 CONVENTIONALMIXER TOPOLOGY......Page 324
17.5.2 ALTERNATIVEMIXER TOPOLOGY......Page 325
17.5.3 LINEARIZATION TECHNIQUE......Page 328
17.5.4 TYPICAL PERFORMANCE......Page 329
REFERENCES......Page 331
18.1 INTRODUCTION......Page 333
18.2.1 BASIC BIAS CIRCUIT TOPOLOGY......Page 335
18.2.2 BIASDRIVE AND AM-AM/AM-PM CHARACTERISTICS......Page 338
18.2.3 BIAS CIRCUITS AND AM-AM/AM-PM CHARACTERISTICS......Page 340
18.3 RECENT POWER AMPLIFIER TECHNOLOGIES......Page 344
18.3.1 PARALLEL AMPLIFIER APPROACH......Page 345
18.3.2 LOW-REFERENCE-VOLTAGE OPERATION POWER AMPLIFIER......Page 347
REFERENCES......Page 352
19.1 INTRODUCTION......Page 357
19.2 DIGITAL–RF CONVERSION......Page 359
19.3 deltasigma SYSTEM ARCHITECTURE......Page 360
19.4 LC BANDPASS FILTER DESIGN......Page 361
19.4.3 RESONATOR DESIGN......Page 363
19.4.4 PROTOTYPE 5.25 GHZ FILTER DESIGN......Page 365
19.4.5 AUTOMATIC TUNING LOOP......Page 366
19.4.6 DIGITAL TUNING LOOP......Page 367
19.4.7 Q-ENHANCEMENT......Page 368
19.5 EXPERIMENTAL RESULTS......Page 370
19.6 APPLICATIONS FOR WIDEBAND DIGITAL–RF MODULATION......Page 371
REFERENCES......Page 374
20.1 INTRODUCTION......Page 377
20.2 SINGLE-CHIP RECEIVER SOC TOP LEVEL......Page 378
20.3 SPUR COUPLING IN MIXED-SIGNAL SINGLE-CHIP RECEIVER SoCS......Page 379
20.4 FRONT-END LNA SPUR REDUCTION......Page 382
20.5 LNA–MIXER INTERFACE SPUR REDUCTION......Page 383
20.6 RF FREQUENCY SYNTHESIZER SPUR REDUCTION......Page 384
20.7 LOW-NOISE, HIGH-SUPPLY REJECTION REGULATORS......Page 392
20.8 LO PATH SPUR REJECTION......Page 398
20.9 QUADRATURE GENERATOR SPUR REDUCTION......Page 400
20.10 IF PATH SUPPLY SPUR REMIXING......Page 401
20.11 DIGITAL CORE CLOCK GENERATION AND SPUR MANAGEMENT TECHNIQUES......Page 403
20.12 ADC SPUR REDUCTION......Page 405
20.13 DIGITAL REGULATOR WITH HIGH-REVERSE REJECTION RATIO......Page 406
20.14 SHIELDING CONSIDERATIONS OF SENSITIVE SIGNAL LINES......Page 407
20.15 DIGITAL CONTROL LINES SPUR AND NOISE REJECTION......Page 408
20.16 CONCLUSIONS......Page 409
REFERENCES......Page 410
21.1 INTRODUCTION......Page 413
21.2 MISMATCHES IN DIGITAL-TO-RF-AMPLITUDE CONVERTER......Page 417
21.3 MISMATCHES IN DIGITALLY CONTROLLED OSCILLATOR......Page 422
21.3.1 VARACTOR STRUCTURE IN NANOSCALE CMOS......Page 423
21.3.2 FULLY DIGITAL CONTROL OF A CMOS OSCILLATOR......Page 424
21.3.3 MODELING OF VARACTOR MISMATCHES......Page 425
21.3.4 ASSESSMENT OF PHYSICAL DEVICE MISMATCHES......Page 426
REFERENCES......Page 430
22.1 INTRODUCTION......Page 433
22.2 APPLICATIONS......Page 434
22.2.2 SERIAL LINKS OVER BACKPLANES......Page 435
22.3.1 LINEAR TWO-PORT NETWORKS......Page 436
22.3.2 THE TRANSMISSION LINE......Page 438
22.3.3 COMPLETE LINKS......Page 439
22.4.1 TRANSMIT EQUALIZATION......Page 441
22.4.2 RECEIVE EQUALIZATION......Page 443
22.4.3 CROSSTALK......Page 444
22.5.1 SERIAL LINKS......Page 445
22.6 CONCLUSION......Page 446
22.A.3 SCATTERING PARAMETERS......Page 447
REFERENCES......Page 448
23.1 INTRODUCTION......Page 451
23.2 INJECTION-LOCKED CDR CIRCUIT......Page 452
23.3 PHASE-LOCKED CDR CIRCUIT......Page 453
23.3.1.2 Binary PD......Page 454
23.3.2.1 Linear PD......Page 455
23.3.2.2 Binary PD......Page 456
23.3.3 AIDED FREQUENCY ACQUISITION......Page 457
23.4 PHASE-ROTATING CDR CIRCUIT......Page 458
23.5 FULLY DIGITAL CDR CIRCUIT......Page 460
23.6 LC OSCILLATORS IN CDR CIRCUITS......Page 462
23.7 JITTER IN CDR CIRCUITS......Page 464
REFERENCES......Page 466
CONTENTS......Page 471
24.1 INTRODUCTION......Page 472
24.2 SMART CMOS IMAGE SENSOR ARCHITECTURE......Page 473
24.2.1 ACTIVE PIXEL SENSOR PIXEL ARRAY......Page 474
24.2.3 ANALOG FRONT END......Page 475
24.2.5 REFERENCE CIRCUITS......Page 476
24.3 SOURCES OF POWER DISSIPATION IN IMAGE SENSORS......Page 477
24.3.1 SENSOR ARRAY POWER DISSIPATION......Page 478
24.3.2 POWER DISSIPATION IN SCANNING CIRCUITRY......Page 480
24.3.3 ANALOG FRONT END POWER DISSIPATION......Page 481
24.3.6 POWER DISSIPATION IN DIGITAL TIMING AND CONTROL BLOCK......Page 482
24.3.7 POWER DISSIPATION IN IMAGE PROCESSING......Page 483
24.4.1.1 General Considerations......Page 484
24.4.1.2 Practical Example—Self-Powered Active Pixel Sensors......Page 485
24.4.2.1 General Considerations......Page 488
24.4.2.2 Practical Example—Sensor for Multiple Targets Detection and Tracking......Page 489
24.4.3.1 Leakage Control......Page 491
24.4.3.4 Optimization of Sensor Output Chains......Page 492
24.4.3.5 Practical Example—Wide Dynamic Range Snapshot APS......Page 493
REFERENCES......Page 495
25.2.1 PASSIVE PIXEL......Page 499
25.2.2 ACTIVE 3T PIXEL......Page 500
25.2.3 ACTIVE 4T PIXEL......Page 502
25.2.4 GLOBAL SHUTTER AND SPECIALTY PIXELS......Page 503
25.3.1 STATIC STATE......Page 505
25.3.2 PHOTODIODE RESET......Page 506
25.3.3 PHOTOINTEGRATION......Page 507
25.3.4 CORRELATED DOUBLE SAMPLE READOUT......Page 509
25.4 PIXEL SCALING......Page 510
25.4.1 SCALING AND OPTICAL TRANSMISSION......Page 511
25.4.2 SCALING AND SIGNAL CAPACITY......Page 512
25.4.3 PIXEL SCALING AND NOISE......Page 514
REFERENCES......Page 515
26.1 INTRODUCTION......Page 517
26.2 MOTIVATION......Page 518
26.3 LOGARITHMIC PIXELS......Page 519
26.4 LOGARITHMIC PIXELS WITH RESET......Page 524
26.5 INTEGRATING PIXELS WITH A LOGARITHMIC RESPONSE......Page 527
26.6 THE FUTURE......Page 531
REFERENCES......Page 533
27.1 INTRODUCTION......Page 535
27.2 BLOCK-MATRIX AND CONVOLUTIONAL TRANSFORMS......Page 536
27.2.1 DISCRETE WAVELET TRANSFORM: HAAR WAVELET EXAMPLE......Page 537
27.3 ARCHITECTURE......Page 539
27.4 IMAGE ACQUISITION......Page 540
27.5.1 SIGN UNIT......Page 542
27.5.2 deltasigma-MODULATEDMULTIPLYING ADC......Page 543
27.5.3 deltasigma-MODULATED WEIGHTED AVERAGING ADC......Page 544
27.5.4 SWITCH MATRIX......Page 546
27.6 COMPARATIVE EXAMPLE......Page 547
27.7 RESULTS......Page 548
REFERENCES......Page 551
28.1 INTRODUCTION......Page 553
28.2.1 3D GRAPHICS PIPELINE......Page 554
28.2.2 STANDARD APIS FOR HANDHELD 3D GRAPHICS......Page 555
28.3 COMPUTER ARITHMETIC FOR HANDHELD GPUs......Page 556
28.3.1 FLOATING POINT ARITHMETIC......Page 557
28.3.2 FIXED POINT ARITHMETIC......Page 559
28.4 PHILOSOPHY OF UNIFIED COMPUTER ARITHMETIC......Page 560
28.5.1 FIXED POINT HYBRID NUMBER SYSTEM......Page 561
28.5.2.1 Logarithmic Converter......Page 562
28.5.3 FXP-HNS UNIFIED ARITHMETIC UNIT......Page 563
28.5.3.1 Vector Operations......Page 565
28.5.3.2 Elementary Functions......Page 567
28.5.4 EVALUATIONS......Page 571
REFERENCES......Page 573
29.1 INTRODUCTION......Page 575
29.2.1 NOISE......Page 576
29.2.3 GAIN VARIATION......Page 577
29.3.1 SENSOR TECHNIQUES......Page 578
29.3.2 CHOPPER STABILIZATION......Page 579
29.3.3 CORRELATED DOUBLE SAMPLING......Page 580
29.3.5 TEMPERATURE COMPENSATION......Page 581
29.4.2 NONIDEALITIES IN HALL SENSORS......Page 582
29.5.1 ACCELEROMETERS AND GYROSCOPES......Page 583
29.5.2 CIRCUIT TECHNIQUES......Page 585
REFERENCES......Page 586
30.1 INTRODUCTION......Page 589
30.2.2 DETECTOR GEOMETRY......Page 590
30.3 REQUIREMENTS AND LIMITATIONS OF THE FRONT-END ELECTRONICS FOR DIGITAL X-RAY IMAGING......Page 591
30.4.1 NOISE OPTIMIZATION......Page 593
30.4.2 RESET BLOCK......Page 597
30.5 SHAPER STAGE......Page 599
30.6 ANALOG-TO-DIGITAL CONVERSION IN MULTICHANNEL IC......Page 600
30.7.1 CROSSTALK IN MIXED-MODE IC......Page 602
30.7.2 MATCHING PERFORMANCE......Page 603
30.8.1 DEDIX IC—FAST DIGITAL X-RAY IMAGING......Page 605
30.8.2 PEAK DETECTOR DERANDOMIZER ASIC......Page 607
30.8.3 MEDIPIX2 IC......Page 608
30.8.4 PILATUS IC......Page 610
REFERENCES......Page 611
31.1 INTRODUCTION......Page 615
31.1.2 APPLICATIONS OF MEMS GYROSCOPES......Page 616
31.2.1.1 Scale Factor......Page 617
31.3 REVIEW OF MICROMACHINED GYROSCOPES......Page 618
31.4 ELECTRONIC CONTROL SYSTEMS IN GYROSCOPES......Page 620
31.4.4 SENSE CHANNEL......Page 622
31.5 CASE STUDY—MODE-MATCHED TUNING FORK GYROSCOPE......Page 623
31.5.1 CHALLENGES AND TRADE-OFFS IN MICROGYRO INTERFACING......Page 624
31.5.2 REVIEW OF MICROGYRO FRONT-ENDS......Page 625
31.5.3 TRANSIMPEDANCE FRONT-ENDS FOR MOTIONAL CURRENT DETECTION......Page 626
31.5.4.1 Design Considerations......Page 627
31.5.4.2 Characterization Results......Page 629
31.5.5 DRIVE AND SENSE CHANNELS......Page 630
31.5.5.1 System Integration......Page 632
31.6 FUTURE DIRECTIONS AND CONCLUSIONS......Page 633
REFERENCES......Page 635
32.1 INTRODUCTION......Page 637
32.2 ANALOG FRONT-END CHIP ARCHITECTURE......Page 639
32.2.1 READ CHANNEL......Page 640
32.2.2 THE MODELING APPROACH......Page 641
32.3 CANTILEVER MODEL......Page 642
32.3.1 ELECTRICAL/THERMAL MODEL......Page 644
32.3.2 MECHANICAL/ELECTROSTATIC MODEL......Page 646
32.4.2 ELECTROSTATIC/MECHANICAL MODEL......Page 649
32.5.1 INPUT STAGE......Page 651
32.5.2 MODEL-BASED OPTIMIZATION OF POWER/SIGNAL-TO-NOISE RATIO......Page 652
32.6 EXPERIMENTAL RESULTS......Page 654
REFERENCES......Page 655