Circuit and Interconnect Design for RF and High Bit-Rate Applications

0387471006......Page 1
Contents......Page 6
Preface......Page 10
1. The Challenge......Page 14
1.1 Interconnect......Page 19
1.2 Device Metrics......Page 21
1.3 Cross-Connect Switches......Page 23
1.4 Transistor Operation above BV[sub(CEO)]......Page 26
1.5 CML Circuits, PRBS Generator......Page 29
1.6 Oscillators......Page 32
1.7 Outline of the Book......Page 34
References......Page 36
2.1 Introduction......Page 38
2.2.1 Single-Ended Lines......Page 42
2.2.2 Differential Lines......Page 47
2.3 When to Include Transmission Line Effects......Page 50
2.4 Secondary Effects......Page 51
2.4.2 Effect of the Substrate; Slow-Wave Effects......Page 52
2.4.3 Skin Effect......Page 55
2.5 Resistivity-Frequency Mode Chart for a Microstrip Line......Page 60
2.6 Preferred Transmission Line Configurations......Page 64
2.7 Applying the Skin Effect Formulas to a SiGe BiCMOS Process......Page 66
2.8 Models Including Skin Effect......Page 68
2.9 Signal Transfer Across a Transmission Line......Page 70
2.10 Interconnect Test Structures......Page 71
2.10.1 Single-Ended Transmission Line......Page 72
2.10.2 Differential Transmission Line......Page 74
2.11 Modelling and Considerations of Digital Interconnect......Page 81
2.12 Circuit and Interconnect Design Flow......Page 82
2.13 Conclusions and Outlook......Page 83
References......Page 85
3.1 Introduction......Page 87
3.2 Miller Effects......Page 89
3.3 Definitions Based on y-Parameters......Page 90
3.3.1 Unity Current Gain Bandwidth f[sub(T)]......Page 91
3.3.2 Input Bandwidth f[sub(V)]......Page 93
3.3.3 Output Bandwidth f[sub(out)] and Available Bandwidth f[sub(A)]......Page 94
3.3.4 Negative Resistance of a Cross-Coupled Differential Pair f[sub(cross)]......Page 97
3.3.5 Maximum Oscillation Frequency f[sub(max)]......Page 99
3.4 Approximate Formulas for the Device Metrics......Page 101
3.4.1 Approximation for f[sub(T)]......Page 103
3.4.3 Approximation for f[sub(out)]......Page 104
3.4.4 Approximation for f[sub(A)]......Page 106
3.4.5 Approximation for f[sub(cross)]......Page 109
3.4.6 Approximation for f[sub(max)]......Page 110
3.5 Optimising a Technology for f[sub(A)]......Page 113
3.6 Relationship between f[sub(A)], f[sub(T)] and f[sub(max)]......Page 118
3.7.1 Trends Relating to Device Metrics......Page 120
3.7.2 Self-Heating......Page 123
3.8 Other Trends......Page 125
3.9 Bipolar Versus RF-CMOS......Page 126
3.10 Conclusions and Outlook......Page 127
References......Page 128
4.1 Introduction......Page 131
4.2 Switch Matrix Design......Page 133
4.2.2 The Concept of Distributed Capacitive Loading......Page 134
4.2.3 Matrix Node Circuit Design......Page 136
4.2.4 Cross-Connect Switch IC Floorplan......Page 144
4.3.1 Intermediate Buffer Circuits......Page 148
4.3.2 Input and Output Buffer Circuits......Page 149
4.4.1 Small-Signal Simulations......Page 150
4.4.2 Large-Signal Simulations......Page 153
4.5 Supply Decoupling......Page 154
4.6 Experimental Results......Page 157
4.7 Conclusions and Outlook......Page 160
References......Page 162
5.1 Introduction......Page 164
5.2 Principle of Collector-Base Avalanche Current......Page 166
5.3 Analysis of Simple 2-Transistor Current Mirrors......Page 169
5.4 Analysis of Current Mirrors with Internal Buffer......Page 172
5.5.1 Feedforward Techniques......Page 174
5.5.2 Feedback Techniques......Page 177
5.6 Conclusions and Outlook......Page 181
References......Page 185
6.1 Introduction......Page 186
6.2 PRBS Background......Page 187
6.3 InP Technology......Page 190
6.4.1 PRBS Generator Block Diagram......Page 192
6.4.2 All-Zero Detection and Correction......Page 195
6.4.3 Clock Distribution and Latch Design......Page 196
6.5 Experimental Results......Page 202
6.6 Distributed Capacitive Loading Reviewed......Page 204
6.7 Conclusions and Outlook......Page 205
References......Page 207
7.1 Introduction......Page 208
7.2 Input Impedance of a Cross-Coupled Differential Pair......Page 210
7.3 Input Impedance of a Capacitively Loaded Emitter Follower......Page 213
7.4 Combining Negative Resistance and Output Buffer Functions......Page 215
7.5 LC-VCO Operating at a Frequency Close to f[sub(cross)]......Page 218
7.5.1 Inductor and Varactor......Page 219
7.5.2 VCO and Output Buffer Circuits......Page 221
7.5.3 Experimental Results......Page 223
7.6.1 Inductor and Varactor......Page 227
7.6.2 VCO and Output Buffer Circuits......Page 229
7.6.3 Experimental Results......Page 230
7.7 I/Q Signal Generation......Page 235
7.8 Conclusions and Outlook......Page 243
References......Page 245
Abbreviations......Page 246
Symbols......Page 247
Appendix A: y-parameters for a Transistor Model with Arbitrary R[sub(e)], R[sub(b)] and R[sub(c)]......Page 250
P......Page 255
W......Page 256