Bluetooth 5.0 Modem Design for IoT Devices

Preface
Contents
About the Author
Chapter 1: An Introduction to Bluetooth
	1.1 Bluetooth History
	1.2 Bluetooth Applications
		1.2.1 Handheld Devices
		1.2.2 Wire-Bound Connections
		1.2.3 Headsets
		1.2.4 Internet Access
		1.2.5 Localization
	1.3 Bluetooth Cores and Layers
	1.4 Transmitter Fundamentals
		1.4.1 Mapping
			1.4.1.1 GFSK
			1.4.1.2 π /4 DQPSK
			1.4.1.3 8DPSK
		1.4.2 Pulse Shaping
			1.4.2.1 The Concept of Inter-Symbol Interference (ISI)
			1.4.2.2 Pulse Shaping Techniques
		1.4.3 Modulation (Mixing with Carrier Frequency)
			1.4.3.1 GFSK
			1.4.3.2 M-Ary DPSK
	1.5 Receiver Fundamentals
		1.5.1 Demodulation
		1.5.2 Pulse Shaping
		1.5.3 De-Mapping
	1.6 CORDIC Theory
		1.6.1 Introduction
		1.6.2 Summary of CORDIC Algorithm
	1.7 Digital Filters
		1.7.1 Advantages of Digital Filters
	1.8 Symbol Timing Recovery
		1.8.1 Timing Error Detectors Algorithms
			1.8.1.1 Early-Late Gate Algorithm
			1.8.1.2 Mueller and Muller Algorithm
			1.8.1.3 Gardner Algorithm
	1.9 Carrier Recovery
		1.9.1 Pilot Tone Assisted Carrier Recovery
		1.9.2 Costas Loop
		1.9.3 Decision Feedback Phase Locked Loop
	References
Chapter 2: An Introduction to IoT
	2.1 Introduction
	2.2 IoT Physical Layer
	2.3 IoT Network and Communication Layer
	2.4 IoT Application Layer
	2.5 AI, Big Data and IoT
	2.6 Conclusions
	References
Chapter 3: Hardware Realization of GFSK-Based Bluetooth Modem
	3.1 GFSK Transceiver Overview
	3.2 Survey of GFSK Transceiver Architecture
		3.2.1 GFSK Transmitter Architecture
			3.2.1.1 Direct Modulation
			3.2.1.2 Continuous Phase GFSK Modulation
			3.2.1.3 Quadrature Modulation
		3.2.2 GFSK Receiver Architecture
		3.2.3 Non-Coherent Demodulation
			3.2.3.1 Frequency Discrimination
			3.2.3.2 DLL Based Demodulator
			3.2.3.3 Correlator Demodulator
			3.2.3.4 Band-Pass Filter Based Demodulator
		3.2.4 Coherent Demodulation
			3.2.4.1 Phase Shift Discrimination
	3.3 The Proposed GFSK Transceiver Architecture
		3.3.1 The Proposed GFSK Transmitter
		3.3.2 The Proposed GFSK Receiver
			3.3.2.1 Proposed Timing Recovery Algorithm
	3.4 Simulink Model for GFSK Transceiver
		3.4.1 Simulink Model for GFSK Transmitter
		3.4.2 Simulink Model for Bluetooth GFSK Receiver
		3.4.3 Simulink Simulation Results for GFSK Transceiver
	3.5 HDL Model for GFSK Transceiver
		3.5.1 HDL Model for GFSK Transmitter
			3.5.1.1 HDL Model for the Numerically Controlled Oscillator (NCO)
				The Numerically Controlled Oscillator Building Blocks
				HDL Simulation Results for NCO
			3.5.1.2 HDL Model for Gaussian Filter
		3.5.2 HDL Model for GFSK Receiver
			3.5.2.1 HDL Model for ARCTAN Function
				HDL Simulation Results for ARCTAN Block
			3.5.2.2 HDL Model for Low Pass Filter
			3.5.2.3 HDL Model for Timing Recovery
		3.5.3 HDL Simulation Results for GFSK Transceiver
	3.6 Conclusion
	References
Chapter 4: Hardware Realization of DPSK-Based Bluetooth Modem
	4.1 DPSK Transceiver Overview
	4.2 Proposed DPSK Transceiver Architecture
		4.2.1 Proposed DPSK Transmitter Architecture
			4.2.1.1 π /4-DQPSK Mapping
			4.2.1.2 8DPSK Mapping
		4.2.2 The Proposed DPSK Receiver Architecture
		4.2.3 Proposed DPSK Carrier Recovery Algorithm
		4.2.4 Proposed DPSK Timing Recovery Algorithm
	4.3 Simulink Model for 8DPSK Transceiver
		4.3.1 Simulink Model for Bluetooth DPSK Transmitter
		4.3.2 Simulink Model for Bluetooth DPSK Receiver
		4.3.3 Simulink Simulation Results for DPSK Transceiver
			4.3.3.1 π/4-DQPSK Simulink Simulation Results
				8DPSK Simulink Simulation Results
	4.4 VHDL Model for DPSK Transceiver
		4.4.1 VHDL Model for DPSK Transmitter
			4.4.1.1 VHDL Model for Square Root Raised Cosine Filter
		4.4.2 VHDL Model for DPSK Receiver
			4.4.2.1 VHDL Model for Carrier Recovery
			4.4.2.2 VHDL Simulation Results for DPSK Transceiver
	4.5 Conclusion
	References
Chapter 5: Verification of the Integrated Bluetooth Modem
	5.1 The Transceiver Block Diagram
	5.2 Simulink Model for the Transceiver
	5.3 VHDL Model for the Transceiver
		5.3.1 Linear Feedback Shift Register
		5.3.2 VHDL Simulation Results for the Transceiver
		5.3.3 Synthesis Results of the Transceiver
	5.4 Verification Strategy
		5.4.1 Simulation Verification
		5.4.2 Hardware Verification
			5.4.2.1 Xilinx Chip-Scope Verification Test
	5.5 Tests Results
	5.6 Conclusion
	References
Chapter 6: Conclusions
Index