Automated Calibration of Modulated Frequency Synthesizers

Contents......Page 6
List of Figures......Page 10
List of Tables......Page 16
Acknowledgments......Page 22
1. INTRODUCTION......Page 24
1.2 Choice of Modulation Affects Battery Life......Page 25
1.3.1 Linear Modulation......Page 26
1.4 GFSK and GMSK......Page 27
1.5 Coherent Versus Noncoherent Demodulation......Page 29
1.5.1 Modulator Requirements for Coherent Detection......Page 32
1.6 Chapter 1 Summary......Page 35
2.1 Direct VCO Modulation......Page 36
2.2 Quadrature Modulator......Page 37
2.3 Open Loop Modulation with PLL Tuning......Page 38
2.4 Modulated Fractional–N Synthesizer......Page 39
2.5 Calibrated Synthesizer Architecture......Page 41
2.6 Chapter 2 Summary......Page 42
3.1 Total Phase Error Variance......Page 44
3.2 Chapter 3 Summary......Page 51
4. AUTOMATIC CALIBRATION SYSTEM......Page 54
4.1 PLL Mismatch Model......Page 55
4.2 The Gain Error Detector......Page 59
4.3 Track and Hold Modification to the Error Detector......Page 61
4.4 Simulated Gain Error Detector Performance......Page 63
4.5.1 Sources of Carrier Phase Error......Page 66
4.5.2 Effect of Phase Offset and Drift on the Gain Error Detector......Page 69
4.5.3 Digital Phase Locked Loop Addition......Page 70
4.6 Complete Gain Error Detector......Page 71
4.7 Acquisition Range and Digital Coarse Calibration......Page 72
4.8 Application to Other Architectures......Page 77
4.9 Chapter 4 Summary......Page 78
5.1 Discrete Prototype......Page 80
5.1.1 Charge Pump and Loop Filter......Page 81
5.1.2 VCO......Page 82
5.1.3 RF Output Filter and Buffer......Page 83
5.1.5 Quadrature Sampler Approach......Page 84
5.1.6 Board Level Phase Quantizer Circuit Details......Page 87
5.1.7 Digital Calibration DAC......Page 88
5.1.8 Multimodulus Divider......Page 89
5.1.9 Reference Oscillator......Page 90
5.2 Integrated Circuit Process Technology......Page 91
5.2.1 Varactor......Page 93
5.2.2 Bondwire Inductors......Page 95
5.3 RF Phase Quantizer......Page 97
5.3.1 RF Phase Quantizer Circuit Details......Page 98
5.3.2 Phase Quantizer Comments......Page 102
5.3.3 RF Interconnect......Page 103
5.4.1 Flip–Flops......Page 105
5.5 Reference Error Filter......Page 106
5.5.1 Decimator Design......Page 110
5.5.2 Discrete Time Filter Approximation......Page 112
5.5.3 Digital Filter Architectures......Page 113
5.5.4 SPT Approximation......Page 117
5.6 Digital Phase Locked Loop and Phase Error Measurement......Page 120
5.6.1 DPLL Loop Dynamics......Page 121
5.6.2 Carrier Phase Detector with Track and Hold......Page 123
5.6.3 Upsampler......Page 127
5.7 Gain Control Multiplier and Error Amp......Page 128
5.9 Main Synthesizer......Page 129
5.10 Σ–Δ Modulator......Page 131
5.11 Chapter 5 Summary......Page 132
6.1.1 Discrete Prototype GFSK/GMSK Eye Pattern and Spectrum......Page 134
6.1.2 Discrete Prototype RF Phase Quantizer......Page 137
6.2 Integrated Circuit Test Environment......Page 138
6.3.1  GFSK/GMSK Eye Pattern and Spectrum......Page 141
6.3.2  4 Level GFSK Eye Pattern and Spectrum......Page 143
6.3.3  Calibration Dynamics......Page 144
6.5 VCO performance......Page 146
6.6 RF Phase Quantizer......Page 154
6.7 Summary......Page 155
7. SUMMARY AND CONCLUSIONS......Page 160
7.1 Recommendations for Future Work......Page 161
A. 1 Simulation Tools......Page 168
A. 3 Typesetting Tools......Page 169
A. 4 Miscellaneous......Page 170
Index......Page 172