Arithmetic Built-In Self-Test for Embedded Systems

Arithmetic Built-in Self-Test for Embedded Systems......Page 1
Contents......Page 4
Preface......Page 8
1.1 Introduction......Page 14
1.2.1 Controllability and Observability......Page 17
1.2.2 Ad Hoc Techniques......Page 19
1.2.3 Scan Designs......Page 21
1.2.4 Boundary-Scan Architecture......Page 25
1.2.5 Test Point Insertion......Page 27
1.3.2 Pseudo-Exhaustive Testing......Page 30
1.3.3 Pseudo-Random Testing......Page 32
1.3.4 Weighted Patterns......Page 36
1.3.5 Reseeding of Linear Feedback Shift Registers......Page 37
1.3.6 Diffraction......Page 41
1.3.8 Scan-Encoded Patterns......Page 43
1.4.1 Objectives and Requirements......Page 45
1.4.2 Compaction Schemes......Page 46
1.4.3 Error Models and Aliasing......Page 48
1.5.1 Design Rules for BIST......Page 51
1.5.2 Serial BIST Architectures......Page 55
1.5.3 Parallel BIST Architectures......Page 57
1.5.4 BIST controllers......Page 60
1.5.5 Modular BIST......Page 62
1.5.6 Automation of BIST......Page 65
1.6 BIST for Memory Arrays......Page 66
1.6.1 Schemes Based on Deterministic Tests......Page 68
1.6.3 Transparent BIST......Page 70
2.1 Additive Generators of Exhaustive Patterns......Page 74
2.1.1 Basic Notions......Page 75
2.1.2 Optimal Generators for Single Size Subspaces......Page 78
2.1.3 Operand Interleaving......Page 83
2.1.4 The Best Generators for Subspaces Within a Range of Sizes......Page 85
2.2.1 Emulation of LFSRs and CAs......Page 89
2.2.2 Weighted Patterns......Page 90
2.2.3 Generators for Delay Testing......Page 92
2.3 Two-Dimensional Generators......Page 94
3. Test-Response Compaction......Page 100
3.1 Binary Adders......Page 101
3.2.1 Steady State Analysis......Page 103
3.2.2 Transient Behavior......Page 106
3.2.3 Detection of Internal Faults......Page 113
3.3 Rotate-Carry Adders......Page 114
3.3.1 Fault-Free Operation......Page 115
3.3.2 Test-Response Compaction......Page 117
3.3.3 The Compaction Quality......Page 121
3.4 Cascaded Compaction Scheme......Page 125
4.1 Analytical Model......Page 130
4.2 Experimental Validation......Page 134
4.3 The Quality of Diagnostic Resolution......Page 135
4.4 Fault Diagnosis in Scan-Based Designs......Page 139
5.1 Testing of ALU......Page 148
5.1.2 Test Application Phase......Page 150
5.1.4 Experimental Validation......Page 152
5.2 Testing of the MAC Unit......Page 153
5.3 Testing of the Microcontroller......Page 154
6. Fault Grading......Page 160
6.1 Fault Simulation Framework......Page 161
6.2 Functional Fault Simulation......Page 163
6.2.1 Ripple-Carry Adder......Page 165
6.2.3 Carry-Lookahead Adder......Page 166
6.2.6 Array Multiplier......Page 167
6.2.7 Booth Multiplier......Page 172
6.3 Experimental Results......Page 176
6.3.1 Performance of Building Block Models......Page 177
6.3.2 High-Level Synthesis Benchmark Circuits......Page 178
6.3.3 Comparison with PROOFS......Page 179
7. High-Level Synthesis......Page 186
7.1.2 Carry-Lookahead Adder......Page 187
7.1.3 Carry-Skip Adder......Page 188
7.2 Synthesis Steps......Page 189
7.3 Simulation Results......Page 191
8.1.1 Pseudo-Random Testing......Page 198
8.1.2 Deterministic Testing......Page 200
8.2.1 Test program......Page 205
8.2.3 Read and Write Logic Faults......Page 207
8.2.5 Multiple Faults......Page 208
8.3 Digital Integrators......Page 209
8.3.1 Testing of the Unmodified Integrator......Page 210
8.3.2 Modified Integrator......Page 212
8.3.3 Register File-Based Integrator......Page 216
8.4 Leaking Integrators......Page 220
8.4.1 Unidirectional Faults......Page 221
8.4.2 Bidirectional Faults......Page 228
8.4.3 An Improved Compaction Scheme......Page 231
9. Epilog......Page 236
Appendix A - Tables of Generators......Page 240
Appendix B - Assembly Language......Page 258
Bibliography......Page 262
Index......Page 278
Back cover......Page 282