Applied Reconfigurable Computing: 13th International Symposium, ARC 2017, Delft, The Netherlands, April 3-7, 2017, Proceedings

Front Matter....Pages I-XX
Front Matter....Pages 1-1
Improving the Performance of Adaptive Cache in Reconfigurable VLIW Processor....Pages 3-15
NIM: An HMC-Based Machine for Neuron Computation....Pages 16-27
VLIW-Based FPGA Computation Fabric with Streaming Memory Hierarchy for Medical Imaging Applications....Pages 28-35
Front Matter....Pages 36-43
Hardware Sandboxing: A Novel Defense Paradigm Against Hardware Trojans in Systems on Chip....Pages 45-45
Rapid Development of Gzip with MaxJ....Pages 47-59
On the Use of (Non-)Cryptographic Hashes on FPGAs....Pages 60-71
An FPGA-Based Implementation of a Pipelined FFT Processor for High-Speed Signal Processing Applications....Pages 72-80
Front Matter....Pages 81-89
Soft Timing Closure for Soft Programmable Logic Cores: The ARGen Approach....Pages 91-91
FPGA Debugging with MATLAB Using a Rule-Based Inference System....Pages 93-105
Hardness Analysis and Instrumentation of Verilog Gate Level Code for FPGA-based Designs....Pages 106-117
A Framework for High Level Simulation and Optimization of Coarse-Grained Reconfigurable Architectures....Pages 118-128
Front Matter....Pages 129-137
Parameter Sensitivity in Virtual FPGA Architectures....Pages 139-139
Custom Framework for Run-Time Trading Strategies....Pages 141-153
Exploring HLS Optimizations for Efficient Stereo Matching Hardware Implementation....Pages 154-167
Architecture Reconfiguration as a Mechanism for Sustainable Performance of Embedded Systems in case of Variations in Available Power....Pages 168-176
Front Matter....Pages 177-186
Exploring Performance Overhead Versus Soft Error Detection in Lockstep Dual-Core ARM Cortex-A9 Processor Embedded into Xilinx Zynq APSoC....Pages 187-187
Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs....Pages 189-201
Front Matter....Pages 202-213
FPGA Applications in Unmanned Aerial Vehicles - A Review....Pages 215-215
Genomic Data Clustering on FPGAs for Compression....Pages 217-228
Front Matter....Pages 229-240
A Quantitative Analysis of the Memory Architecture of FPGA-SoCs....Pages 215-215
Front Matter....Pages 241-252
Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms....Pages 253-253
An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning....Pages 255-267
Accuracy Evaluation of Long Short Term Memory Network Based Language Model with Fixed-Point Arithmetic....Pages 268-280
FPGA Implementation of a Short Read Mapping Accelerator....Pages 281-288
Front Matter....Pages 289-296
dfesnippets: An Open-Source Library for Dataflow Acceleration on FPGAs....Pages 297-297
A Machine Learning Methodology for Cache Recommendation....Pages 299-310
ArPALib: A Big Number Arithmetic Library for Hardware and Software Implementations. A Case Study for the Miller-Rabin Primality Test....Pages 311-322
Back Matter....Pages 323-330
....Pages 331-332