An Engineer's Guide to Automated Testing of High-Speed Interfaces

An Engineer’s Guide to Automated Testing of High-Speed Interfaces......Page 2
Contents......Page 8
Preface......Page 18
Acknowledgments......Page 20
1 Introduction......Page 22
1.1 Characterization and Design Verification......Page 23
1.2 Production Testing......Page 25
1.4 The ATE Test Fixture......Page 26
References......Page 28
2.1 High-Speed Digital Signaling......Page 30
2.1.1 Out-of-Band Signaling......Page 31
2.1.2 Data Eye Diagram......Page 32
2.1.3 Differential Signaling......Page 33
2.1.4 Transmission Line Termination......Page 35
2.2 Time and Frequency Domains......Page 38
2.2.1 The Concept of Bandwidth and Its Pitfalls......Page 39
2.3 Bit Error Rate......Page 42
2.4 Jitter......Page 44
2.4.1 Jitter Histogram......Page 46
2.4.2 Jitter Categorization......Page 47
2.4.3 Amplitude Noise and Conversion to Timing Jitter......Page 55
2.4.4 Jitter in the Frequency Domain......Page 57
2.5 Classification of High-Speed I/O Interfaces......Page 60
2.6.1 Phase Locked Loop (PLL)......Page 64
2.6.3 Clock and Data Recovery (CDR)......Page 67
2.6.4 Pre-Emphasis/De-Emphasis and Equalization......Page 70
References......Page 74
3 High-Speed Interface Standards......Page 76
3.1.2 PCI Express Fundamentals......Page 77
3.1.3 PCI Express Details......Page 80
3.1.4 PCI Express Protocol......Page 82
3.1.5 Electrical Specifications......Page 86
3.1.6 ATE Test Requirements......Page 89
3.1.7 Test Support......Page 91
3.1.8 Test Challenges\r......Page 92
3.2.1 Application Areas......Page 94
3.2.2.1 Data Link Layer......Page 95
3.2.2.2 Physical Layer......Page 97
3.2.3 Electrical Specifications......Page 104
3.2.5 Test Requirements......Page 106
3.2.6 Test Challenges......Page 112
3.3.2 XDR Fundamentals......Page 114
3.3.3 XDR DRAM Details......Page 116
3.3.4 XDR Protocol......Page 120
3.3.5 Electrical Specifications......Page 126
3.3.8 Test Challenges......Page 127
3.4.2 GDDR Fundamentals......Page 128
3.4.3 GDDR5 Details......Page 129
3.4.4 GDDR5 Protocol......Page 135
3.4.5 Electrical Specifications......Page 143
3.4.6 ATE Test Requirements......Page 144
3.4.8 Test Challenges......Page 145
3.5 Other High-Speed Digital Interface Standards......Page 148
References......Page 150
4 ATE Instrumentation for Digital Applications......Page 154
4.1 Digital Pin Electronics ATE Card......Page 158
4.1.1 CDR and Phase Tracking......Page 160
4.1.3 Time Interval Analyzer or Time Stamper......Page 161
4.1.4 Timing Jitter Injection......Page 162
4.1.5 Amplitude Noise and Common Mode Voltage Injection......Page 164
4.1.6 Bidirectional and Simultaneous Bidirectional Support......Page 165
4.1.9 Parametric Measurements......Page 167
4.2.1 Aliasing......Page 171
4.2.2 Digitizer......Page 172
4.2.3 Sampler......Page 173
4.3.1 Undersampling of High-Speed I/O Signals......Page 174
4.3.2 Coherency Equation......Page 176
4.3.3 Capturing Digital Waveforms......Page 177
4.3.4 Special Considerations for Coherent Sampling with Digital ATE Channels......Page 180
4.4 Power Supplies......Page 181
References......Page 183
5.1 Bit and Pattern Alignment......Page 184
5.1.1 Bit Alignment......Page 186
5.1.2 Pattern Alignment......Page 189
5.2 Functional Test......Page 191
5.3 Shmoo Tests......Page 193
5.4.1 Rise/Fall Time......Page 196
5.4.2 Data Eye Diagram......Page 197
5.4.3 BER Bathtub Curve......Page 206
5.4.4 Skew......Page 209
5.4.5 Pre-Emphasis and De-Emphasis Measurement......Page 212
5.5.1 Jitter Histogram......Page 213
5.5.2 RMS Jitter......Page 214
5.5.3 Peak-to-Peak Jitter......Page 215
5.5.4 Measuring the Jitter Spectrum......Page 216
5.5.5 Random and Deterministic Jitter Separation......Page 218
5.5.6 Measuring the Data Dependent Jitter......Page 225
5.5.7 Jitter Measurement Correlation......Page 226
5.5.8 Driver Amplitude Noise......Page 229
5.6.1 Setup and Hold......Page 232
5.6.2 Receiver Sensitivity......Page 233
5.7 Receiver Jitter Tolerance......Page 235
5.7.1 Random Jitter Tolerance......Page 236
5.7.2 Sinusoidal Jitter Tolerance......Page 237
5.7.3 DDJ Jitter Tolerance......Page 239
5.7.4 Testing the Receiver Equalizer......Page 241
5.8.1 Jitter Transfer......Page 242
5.8.2 Frequency Offset......Page 244
5.8.3 Spread Spectrum Clocking......Page 245
5.9.1 Impedance Tests......Page 248
5.9.2 Return Loss......Page 252
5.10 Measurement Errors......Page 254
References......Page 255
6 Production Testing......Page 258
6.1 Golden Device......Page 259
6.3 Instrument-Based Testing: At-Speed ATE......Page 260
6.3.1 Physical Implementation......Page 261
6.3.2 Parametric Testing......Page 263
6.4.1 Double Data Clocking......Page 267
6.4.3 Near-End Loopback Testing......Page 270
6.6 Active Test Fixture......Page 282
6.7 Multisite Testing......Page 283
6.7.1 Driver Sharing for Multisite Applications......Page 284
References......Page 287
7.1.1 Real-Time Oscilloscopes......Page 290
7.1.2 Equivalent-Time Sampling Oscilloscopes......Page 291
7.2 Bit Error Rate Tester......Page 295
7.3 Time Interval Analyzer......Page 296
7.4 Spectrum Analyzer......Page 297
7.6 Arbitrary Waveform and Function Generators......Page 298
7.7 Noise Generators......Page 300
7.8 Sinusoidal Clock Sources......Page 301
7.9.1 Signal Integrity......Page 303
7.9.2 Synchronization......Page 305
7.9.3 External Reference Clock Impact on Jitter Measurements......Page 307
7.10.1 Coaxial Cables......Page 308
7.10.2 Coaxial Connectors......Page 314
7.11.1 Power Splitters and Power Dividers/Combiners......Page 319
7.11.2 Attenuators, Blocking Capacitors, and Terminations......Page 320
7.11.3 Pick-Off T......Page 322
7.11.5 Probes......Page 323
7.11.6 Balun......Page 327
7.11.7 Rise Time Converters......Page 329
References......Page 330
8 Test Fixture Design......Page 332
8.1 Test Fixtures......Page 334
8.2 High-Speed Design Effects......Page 336
8.2.1 Reflections Due to Impedance Mismatches......Page 337
8.2.2 Conductor Losses......Page 340
8.2.3 Dielectric Losses......Page 341
8.2.4 Crosstalk......Page 349
8.3.1 Microstrip and Striplines......Page 351
8.3.2 Differential Routing......Page 354
8.4 Via Transitions......Page 355
8.4.1 Interlayer Vias......Page 360
8.4.2 Pogo Pin Vias......Page 361
8.5 DUT BGA Ballout......Page 363
8.6 Sockets......Page 367
8.6.1 Socket Electrical Characterization......Page 368
8.7 Relays......Page 370
8.8 Bidirectional Layout......Page 375
8.9 Wafer Probing......Page 377
8.10 Stack-Up......Page 380
8.11 Power Distribution Network......Page 384
8.11.1 Power Planes......Page 391
8.11.2 Decoupling Capacitors......Page 396
8.11.3 Socket Inductance......Page 404
8.11.5 Power Distribution Network Simulation......Page 405
References......Page 407
9.1.1 Accuracy and Resolution......Page 412
9.1.2 Understanding OTA and EPA......Page 413
9.1.3 Linearity and Edge Placement Accuracy......Page 414
9.1.4 Calibration......Page 416
9.2 Multiplexing of ATE Channels......Page 420
9.3 Focus Calibration......Page 422
9.3.2 Data Eye Height Calibration......Page 423
9.3.3 Jitter Injection......Page 425
9.3.4 Data Eye Profile......Page 427
9.4 Testing of High-Speed Bidirectional Interfaces with a Dual Transmission Line Approach......Page 430
9.5 Including the DUT Receiver Data Recovery in Driver Tests......Page 435
9.6 Protocol Awareness and Protocol-Based Testing......Page 437
9.7 Testing Multilevel Interfaces with Standard Digital ATE Pin Electronics......Page 442
9.8.1 Signal Path Loss Compensation: De-Embedding......Page 444
9.8.2 Characterization in the Frequency Domain......Page 449
9.8.3 Signal Path Loss Compensation: Equalization......Page 451
9.9 ATE DC Level Adjustments......Page 460
9.9.1 Correction of Force Levels for DUT Input Pins......Page 462
9.9.2 Correction of Levels for DUT Output Pins......Page 463
References......Page 466
A Introduction to the Gaussian Distribution and Analytical Computation of the BER......Page 470
A.1 The Gaussian Distribution......Page 471
A.2 Computation of the BER for a System with Only Gaussian Random Jitter......Page 474
A.3 Computation of the a(BER) Value......Page 477
A.4 Properties of the Error Function erf(x) and Complementary Error Function erfc(x)......Page 479
References......Page 480
B.1 The Dual Dirac Jitter Model......Page 482
B.2 RJ/DJ Separation with the Q-Factor Algorithm......Page 486
References......Page 488
C.1 Pseudo-Random Bit Sequences......Page 490
C.2 Pseudo-Random Word Sequences......Page 491
C.3 Other Important Patterns......Page 493
References......Page 494
D Coding, Scrambling, Disparity, and CRC......Page 496
D.1 Disparity......Page 497
D.2 8B/10B Coding......Page 499
D.3 Scrambling......Page 502
D.4 Error Detection......Page 505
D.4.2 Checksums......Page 506
References......Page 509
E Time Domain Reflectometry and Time Domain Transmission (TDR/TDT)......Page 512
E.1 TDR......Page 513
E.1.1 Measuring the Impedance of a Trace with a TDR......Page 514
E.1.2 Measuring the Round-Trip Delay of a Signal Trace......Page 515
E.1.4 Measuring the Return Loss with a TDR......Page 516
E.2.1 Measuring the Step Response......Page 518
E.2.3 Measuring Crosstalk Using a TDT and an Extra Sampler......Page 519
E.3 Differential TDR/TDT Measurements......Page 520
References......Page 522
F S-Parameters......Page 524
F.1 Simulating and Synthesizing Time-Domain Responses from S-Parameters......Page 530
F.2 S-Parameters of Coupled Differential Pairs and Structures......Page 532
References......Page 534
G.1 Circuit Simulators......Page 536
G.3 2D Planar Field Solvers......Page 539
G.4 Power Integrity......Page 541
G.6 Other Tools......Page 542
References......Page 545
H.1 Measuring the Test Fixture Performance......Page 546
H.1.1 Test Coupons......Page 548
H.1.2 Test Fixture Socket and Socket Via Field Probing......Page 550
H.2 Measuring the Test Fixture Power Distribution Network......Page 556
References......Page 561
I.1 Sinusoidal Jitter Injection Calibration......Page 564
I.1.1 The J1=J0 Bessel Approach......Page 565
I.1.2 The RJ Subtraction Approach......Page 569
I.2 Random Jitter Injection Calibration......Page 572
I.3 ISI Jitter Injection Calibration......Page 576
References......Page 578
About the Authors......Page 580
Index......Page 582