Advances in Computer Systems Architecture: 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007. Proceedings

Front Matter....Pages -
A Compiler Framework for Supporting Speculative Multicore Processors....Pages 1-1
Power-Efficient Heterogeneous Multicore Technology for Digital Convergence....Pages 2-3
StarDBT: An Efficient Multi-platform Dynamic Binary Translation System....Pages 4-15
Unbiased Branches: An Open Problem....Pages 16-27
An Online Profile Guided Optimization Approach for Speculative Parallel Threading....Pages 28-39
Entropy-Based Profile Characterization and Classification for Automatic Profile Management....Pages 40-51
Laplace Transformation on the FT64 Stream Processor....Pages 52-62
Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation....Pages 63-74
Evolution of NAND Flash Memory Interface....Pages 75-79
FCC-SDP: A Fast Close-Coupled Shared Data Pool for Multi-core DSPs....Pages 80-89
Exploiting Single-Usage for Effective Memory Management....Pages 90-101
An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories....Pages 102-113
An Effective Design of Master-Slave Operating System Architecture for Multiprocessor Embedded Systems....Pages 114-125
Optimal Placement of Frequently Accessed IPs in Mesh NoCs....Pages 126-138
An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips....Pages 139-150
Performance of Keyword Connection Algorithm in Nested Mobility Networks....Pages 151-162
Leakage Energy Reduction in Cache Memory by Software Self-invalidation....Pages 163-174
Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for Computational Clusters....Pages 175-185
Runtime Performance Projection Model for Dynamic Power Management....Pages 186-197
A Power-Aware Alternative for the Perceptron Branch Predictor....Pages 198-208
Power Consumption and Performance Analysis of 3D NoCs....Pages 209-219
A Design Methodology for Performance-Resource Optimization of a Generalized 2D Convolution Architecture with Quadrant Symmetric Kernels....Pages 220-234
Bipartition Architecture for Low Power JPEG Huffman Decoder....Pages 235-243
A SWP Specification for Sequential Image Processing Algorithms....Pages 244-255
A Stream System-on-Chip Architecture for High Speed Target Recognition Based on Biologic Vision....Pages 256-267
FPGA-Accelerated Active Shape Model for Real-Time People Tracking....Pages 268-279
Performance Evaluation of Evolutionary Multi-core and Aggressively Multi-threaded Processor Architectures....Pages 280-289
Synchronization Mechanisms on Modern Multi-core Architectures....Pages 290-303
Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs....Pages 304-314
Generalized Wormhole Switching: A New Fault-Tolerant Mathematical Model for Adaptively Wormhole-Routed Interconnect Networks....Pages 315-326
Open Issues in MPI Implementation....Pages 327-338
Implicit Transactional Memory in Kilo-Instruction Multiprocessors....Pages 339-353
Design of a Low–Power Embedded Processor Architecture Using Asynchronous Function Units....Pages 354-363
A Bypass Mechanism to Enhance Branch Predictor for SMT Processors....Pages 364-375
Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-Time SMT Processor....Pages 376-386
Architectural Solution to Object-Oriented Programming....Pages 387-398
Back Matter....Pages -