Advances in Computer Systems Architecture: 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006. Proceedings

Front Matter....Pages -
The Era of Multi-core Chips -A Fresh Look on Software Challenges....Pages 1-1
Streaming Networks for Coordinating Data-Parallel Programs (Position Statement)....Pages 2-5
Implementations of Square-Root and Exponential Functions for Large FPGAs....Pages 6-23
Using Branch Prediction Information for Near-Optimal I-Cache Leakage....Pages 24-37
Scientific Computing Applications on the Imagine Stream Processor....Pages 38-51
Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination....Pages 52-66
A Study of the Performance Potential for Dynamic Instruction Hints Selection....Pages 67-80
Reorganizing UNIX for Reliability....Pages 81-94
Critical-Task Anticipation Scheduling Algorithm for Heterogeneous and Grid Computing....Pages 95-108
Processor Directed Dynamic Page Policy....Pages 109-122
Static WCET Analysis Based Compiler-Directed DVS Energy Optimization in Real-Time Applications....Pages 123-136
A Study on Transformation of Self-similar Processes with Arbitrary Marginal Distributions....Pages 137-146
 μ TC – An Intermediate Language for Programming Chip Multiprocessors....Pages 147-160
Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays....Pages 161-174
Trace-Based Data Cache Leakage Reduction at Link Time....Pages 175-188
Parallelizing User-Defined and Implicit Reductions Globally on Multiprocessors....Pages 189-202
Overload Protection for Commodity Network Appliances....Pages 203-218
An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit....Pages 219-230
A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster....Pages 231-243
Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor....Pages 244-259
Combining Wireless Sensor Network with Grid for Intelligent City Traffic....Pages 260-269
A Novel Processor Architecture for Real-Time Control....Pages 270-280
A 0-1 Integer Linear Programming Based Approach for Global Locality Optimizations....Pages 281-294
Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs....Pages 295-308
Entropy Throttling: A Physical Approach for Maximizing Packet Mobility in Interconnection Networks....Pages 309-322
Design of an Efficient Flexible Architecture for Color Image Enhancement....Pages 323-336
Hypercube Communications on Optical Chordal Ring Networks with Chord Length of Three....Pages 337-343
PMPS(3): A Performance Model of Parallel Systems....Pages 344-350
Issues and Support for Dynamic Register Allocation....Pages 351-358
A Heterogeneous Multi-core Processor Architecture for High Performance Computing....Pages 359-365
Reducing the Branch Power Cost in Embedded Processors Through Static Scheduling, Profiling and SuperBlock Formation....Pages 366-372
Fault-Free Pairwise Independent Hamiltonian Paths on Faulty Hypercubes....Pages 373-379
Constructing Node-Disjoint Paths in Enhanced Pyramid Networks....Pages 380-386
Striping Cache: A Global Cache for Striped Network File System....Pages 387-393
DTuplesHPC: Distributed Tuple Space for Desktop High Performance Computing....Pages 394-400
The Algorithm and Circuit Design of a 400MHz 16-Bit Hybrid Multiplier....Pages 401-408
Live Range Aware Cache Architecture....Pages 409-415
The Challenges of Efficient Code-Generation for Massively Parallel Architectures....Pages 416-422
Reliable Systolic Computing Through Redundancy....Pages 423-429
A Diversity-Controllable Genetic Algorithm for Optimal Fused Traffic Planning on Sensor Networks....Pages 430-436
A Context-Switch Reduction Heuristic for Power-Aware Off-Line Scheduling....Pages 437-444
On the Reliability of Drowsy Instruction Caches....Pages 445-451
Design of a Reconfigurable Cryptographic Engine....Pages 452-458
Enhancing ICOUNT2.8 Fetch Policy with Better Fairness for SMT Processors....Pages 459-465
The New BCD Subtractor and Its Reversible Logic Implementation....Pages 466-472
Power-Efficient Microkernel of Embedded Operating System on Chip....Pages 473-479
Understanding Prediction Limits Through Unbiased Branches....Pages 480-487
Bandwidth Optimization of the EMCI for a High Performance 32-bit DSP....Pages 488-494
Research on Petersen Graphs and Hyper-cubes Connected Interconnection Networks....Pages 495-501
Cycle Period Analysis and Optimization of Timed Circuits....Pages 502-508
Acceleration Techniques for Chip-Multiprocessor Simulator Debug....Pages 509-515
A DDL–Based Software Architecture Model....Pages 516-522
Branch Behavior Characterization for Multimedia Applications....Pages 523-530
Optimization and Evaluating of StreamYGX2 on MASA Stream Processor....Pages 531-537
SecureTorrent: A Security Framework for File Swarming....Pages 538-544
Register Allocation on Stream Processor with Local Register File....Pages 545-551
A Self-reconfigurable System-on-Chip Architecture for Satellite On-Board Computer Maintenance....Pages 552-558
Compile-Time Thread Distinguishment Algorithm on VIM-Based Architecture....Pages 559-566
Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining....Pages 567-573
Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications....Pages 574-580
Automatic Synthesis of Interface Circuits from Simplified IP Interface Protocols....Pages 581-587
An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors....Pages 588-594
An Efficient Approach to Energy Saving in Microcontrollers....Pages 595-601
Back Matter....Pages -