Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling: From the Clock Path to the Data Path

Preface
Acknowledgements
Contents
About the Authors
Chapter 1: Introduction
	1.1 Trends in the Semiconductor Industry
	1.2 Energy Considerations in Power-Limited and Battery-Powered Systems
	1.3 Wide Power-Performance Tradeoff and System Requirements
		1.3.1 Importance of Wide Power-Performance Tradeoff in Duty-Cycled and Always-On Systems
		1.3.2 Wide Voltage Scaling
	1.4 Challenges in Wide Voltage Scaling and Motivation
	1.5 Book Outline
	References
Chapter 2: Reconfigurable Microarchitecures Down to Pipestage and Memory Bank Level
	2.1 Pipestage as Basic Building Block of Synchronous Microarchitectures
		2.1.1 Background on Pipeline Stages and Timing Constraints
		2.1.2 Pipelining for Microarchitecture Speed-Up
	2.2 Elementary Microarchitectures
	2.3 Impact of Logic Depth on Energy
	2.4 Dynamically Adaptable Pipelines
		2.4.1 Wide Dynamic Voltage Frequency Scaling
		2.4.2 Dynamically Adaptable Pipeline
		2.4.3 Run-Time Pipeline Adaptation via Augmented DVFS Look-Up Table
	2.5 Microprocessor Microarchitectures: Opportunities and Challenges Under Reconfiguration
		2.5.1 Wide DVFS in Microprocessors and Considerations at the Application Level
		2.5.2 Control Flow and Hazards in Microprocessor Microarchitectures with Different Pipedepths
		2.5.3 Limitations of Re-pipelining in Existing Microprocessor Architectures
	2.6 Enabling Microarchitectural Reconfiguration in Microprocessors
	2.7 Dynamically Adaptable Time-Interleaved Microprocessors
	2.8 Static Random Access Memory (SRAM)
	2.9 Methods for SRAM Speed-Up via Reconfigurable Array Organization
	2.10 Conclusion
	References
Chapter 3: Automated Design Flows and Run-Time Optimization for Reconfigurable Microarchitecures
	3.1 Prior Art in Reconfigurable Microarchitectures
	3.2 Overview of Systematic Methodologies and Design Flows for Microarchitectural Reconfiguration
	3.3 Automated Design Flow for Pipeline-Level Reconfiguration: Re-pipelining and Retiming (Steps 1–2)
		3.3.1 Re-pipelining (Step 1)
		3.3.2 Retiming (Step 2)
	3.4 Automated Design Flow for Pipeline-Level Reconfiguration: Register Identification (Step 3, Phase I)
		3.4.1 Netlist to Skeleton Graph (Step 3.1, Phase I)
		3.4.2 Weighted Skeleton Graph (Step 3.2, Phase I)
	3.5 Automated Design Flow for Pipeline-Level Reconfiguration: Register Identification in Linear Pipelines (Step 3, Phase II)
	3.6 Automated Design Flow for Pipeline-Level Reconfiguration: Register Identification in Non-linear Pipelines (Step 3, Phase II)
		3.6.1 Graph Feedforward Cutsets and Properties
		3.6.2 Cutset Identification (Step 3.3B)
		3.6.3 Cutset-to-Pipeline Mapping (Step 3.3C)
	3.7 Automated Design Flow for Pipeline-Level Reconfiguration: Bypassable Registers Choice (Step 3, Phase III)
	3.8 Automated Design Flow for Pipeline-Level Reconfiguration: Bypassable Register Replacement (Step 4)
	3.9 Automated Design Flow Extension to Thread-Level Time-Interleaved Reconfiguration
	3.10 SRAM Reconfiguration at the Bank Level
		3.10.1 Design Considerations on Memory Reconfiguration
		3.10.2 Background on Low-Power and Reconfigurable Memories
		3.10.3 Row Aggregation Technique and Reconfiguration for Selective Performance Enhancement Beyond Nominal Voltage
		3.10.4 Embedding Reconfigurable Row Aggregation Through Minor Modifications of Existing Compiled Memories
	3.11 Conclusion
	References
Chapter 4: Case Studies of Reconfigurable Microarchitectures: Accelerators, Microprocessors, and Memories
	4.1 Fast Fourier Transform (FFT) Accelerator
		4.1.1 Microarchitecture and Design of Its Dynamically Adaptable Pipeline Counterpart
		4.1.2 Measurement Results on a Single Die
		4.1.3 Impact of Variations and Comparison of Measurement Results Across Multiple Dice
		4.1.4 Overhead Due to Microarchitecture Reconfiguration
	4.2 Finite Impulse Response Filter (FIR) and Fixed-Point Multiplier
	4.3 Reconfigurable Thread-Level in ARM Cortex Microcontroller and SRAM Row Aggregation
		4.3.1 Reconfigurable Memory with Selective Row Aggregation
		4.3.2 ARM Cortex-M0 Microcontroller
	4.4 Conclusion
	References
Chapter 5: Reconfigurable Clock Networks, Automated Design Flows, Run-Time Optimization, and Case Study
	5.1 Impact of Clock Network Topology on Clock Skew, Performance, and Hold Margin under Wide Voltage Scaling
		5.1.1 Impact of Clock Skew on Performance, Robustness Against Hold Violations, and Energy Efficiency
		5.1.2 Impact of Supply Voltage on Clock Network Optimization and Clock Skew in Conventional Static Clock Networks
		5.1.3 Prior Art in Clock Networks for Low- or Wide-Voltage Operation
	5.2 Reconfigurable Clock Networks: Principles and Fundamentals
	5.3 Bypassable Repeaters and Other Clock Cells
	5.4 Gate-Boostable Clock Root Repeater
	5.5 Automated Design Flows for Reconfigurable Clock Networks and Integration with DVFS
		5.5.1 Automated Clock Tree Design and Level Balance Principle
		5.5.2 Optimal Configuration Selection and Integration with DVFS
	5.6 Case Study: Reconfigurable Clock Network in FFT Accelerator
		5.6.1 Testchip Design
		5.6.2 Clock Skew Measurement Results
		5.6.3 Improvements in Performance, Robustness, and Energy Offered by Reconfigurable Clock Networks
	5.7 Conclusion
	References
Chapter 6: Conclusions
	References
Appendix
	A.1 Pipeline-Level Reconfiguration
	A.2 Thread-Level Reconfiguration
	A.3 Detailed Description of Script I/Os
References
Index